Writing QSPI Flash on MCXN947 board.

[takagi_y]

The other day I asked a question about writing flash to FRDM-MCXN947.

Thanks to your answer, I am now able to write to FRDM-MCXN947.

Thank you.

This time I would like to ask a question about writing flash to another board using MCXN947.

I tried to write to this board using the writing method for FRDM-MCXN947 as a reference, but an error occurred.

Below is the content of the console at that time.

NXP: MCXN947
DAP stride is 1024 bytes (256 words)
Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MCXN9xx_SFDP_FlexSPI.cfx
Image 'MCXN9xx_SFDP_FlexSPI Sep 19 2024 18:18:31'
Opening flash driver MCXN9xx_SFDP_FlexSPI.cfx
VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead.
Using SOFT reset to run the flash driver
Driver V.2 dynamic startup failed - driver Init provided no flash parameters
driver describes no sectors starting at 0x80000000
Flash Driver V.2 startup failed - rc Ef(58): Flash Driver describes no sectors at its base address
chip initialization failed - Ef(58): Flash Driver describes no sectors at its base address
failed to initialize flash driver MCXN9xx_SFDP_FlexSPI.cfx
Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MCXN9xx_SFDP_FlexSPI.cfx
Image 'MCXN9xx_SFDP_FlexSPI Sep 19 2024 18:18:31'
Opening flash driver MCXN9xx_SFDP_FlexSPI.cfx
VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead.
Using SOFT reset to run the flash driver
Driver V.2 dynamic startup failed - driver Init provided no flash parameters
driver describes no sectors starting at 0x80000000
Flash Driver V.2 startup failed - rc Ef(58): Flash Driver describes no sectors at its base address
chip initialization failed - Ef(58): Flash Driver describes no sectors at its base address
failed to initialize flash driver MCXN9xx_SFDP_FlexSPI.cfx

Is there any setting or anything I need to do?

I would appreciate your reply.

[Harry_Zhang]

HI @takagi_y 

"I tried to write to this board using the writing method for FRDM-MCXN947 as a reference, but an error occurred."

You change to another board.

Did you try the same method but not succeed？

BR

Harry

[takagi_y]

Thank you for your reply.

I modified the project with reference to the demo program of FRDM-MCXN947 and confirmed writing from IDE.
The procedure is as written yesterday under "As additional information...".

My board uses MX25L3233F for Flash, so I built an example of CMSIS-DAP Flash Drivers and checked it.

First, I used the one I built without any modifications and wrote it from the IDE. (CONFIG_OPTION0=0xC0000001)
As a result, the following was displayed on the console and writing was not performed.

MCUXpresso IDE RedlinkMulti Driver v24.9 (Sep 19 2024 19:34:05 - crt_emu_cm_redlink build 802)

Found chip XML file in C:/WorkSpace/MCUX/MCUXpressoIDE_24.9.25/NX-N947/frdmmcxn947_hello_world_qspi_xip/Debug\MCXN947.xml

( 5) Remote configuration complete

Reconnected to existing LinkServer process.

Probe Firmware: MCU-LINK (r0FF) CMSIS-DAP V3.153 (NXP Semiconductors)

Serial Number: VUDADS0NIE0ZM

VID:PID: 1FC9:0143

USB Path: 0001:0008:00

Using memory from core 0 after searching for a good core

processor is in secure mode

debug interface type = CoreSight DP (DAP DP ID 6BA02477) over SWD TAP 0

processor type = Cortex-M33 (CPU ID 00000D21) on DAP AP 0

number of h/w breakpoints = 8

number of flash patches = 0

number of h/w watchpoints = 4

Probe(0): Connected&Reset. DpID: 6BA02477. CpuID: 00000D21. Info: <None>

Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled.

Content of CoreSight Debug ROM(s):

RBASE E00FE000: CID B105100D PID 0000095000 ROM (type 0x1)

ROM 1 E00FF000: CID B105100D PID 04000BB4C9 ROM (type 0x1)

ROM 2 E000E000: CID B105900D PID 04000BBD21 CSt ARM ARMv8-M type 0x0 Misc - Undefined

ROM 2 E0001000: CID B105900D PID 04000BBD21 CSt ARM DWTv2 type 0x0 Misc - Undefined

ROM 2 E0002000: CID B105900D PID 04000BBD21 CSt ARM FPBv2 type 0x0 Misc - Undefined

ROM 2 E0000000: CID B105900D PID 04000BBD21 CSt ARM ITMv2 type 0x43 Trace Source - Bus

ROM 2 E0041000: CID B105900D PID 04002BBD21 CSt ARM ETMv4.0 type 0x13 Trace Source - Core

ROM 2 E0042000: CID B105900D PID 04000BBD21 CSt ARM CTIv2 type 0x14 Debug Control - Trigger, e.g. ECT

ROM 1 E0040000: CID B105900D PID 04000BBD21 CSt type 0x11 Trace Sink - TPIU

ROM 1 E0044000: CID B105900D PID 04003BB908 CSt CSTF type 0x12 Trace Link - Trace funnel/router

ROM 1 E0045000: CID B105900D PID 04001BB961 CSt type 0x21 Trace Sink - ETB

NXP: MCXN947

DAP stride is 1024 bytes (256 words)

Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MCXN9xx_SFDP_FlexSPI_.cfx

Image 'MCXN9xx_SFDP_FlexSPI Mar 6 2025 17:01:24'

Opening flash driver MCXN9xx_SFDP_FlexSPI_.cfx

VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead.

Using SOFT reset to run the flash driver

Flash variant 'JEDEC_FlexSPI_Device' detected (0B = at 0x80000000)

driver describes no sectors starting at 0x80000000

Flash Driver V.2 startup failed - rc Ef(58): Flash Driver describes no sectors at its base address

chip initialization failed - Ef(58): Flash Driver describes no sectors at its base address

failed to initialize flash driver MCXN9xx_SFDP_FlexSPI_.cfx

Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MCXN9xx_SFDP_FlexSPI_.cfx

Image 'MCXN9xx_SFDP_FlexSPI Mar 6 2025 17:01:24'

Opening flash driver MCXN9xx_SFDP_FlexSPI_.cfx

VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead.

Using SOFT reset to run the flash driver

Flash variant 'JEDEC_FlexSPI_Device' detected (4MB = 64*64K at 0x80000000)

Closing flash driver MCXN9xx_SFDP_FlexSPI_.cfx

Next, I changed the setting value used in the SEC tool (CONFIG_OPTION0=0xC0000405) and checked, but writing was not performed here either.
(You can write with the SEC tool.)
The following is the console display at that time.

MCUXpresso IDE RedlinkMulti Driver v24.9 (Sep 19 2024 19:34:05 - crt_emu_cm_redlink build 802)

Found chip XML file in C:/WorkSpace/MCUX/MCUXpressoIDE_24.9.25/NX-N947/NX-N947_ledblinky/frdmmcxn947_led_blinky/Debug_NoRAM\MCXN947.xml

( 5) Remote configuration complete

Reconnected to existing LinkServer process.

Probe Firmware: MCU-LINK (r0FF) CMSIS-DAP V3.153 (NXP Semiconductors)

Serial Number: VUDADS0NIE0ZM

VID:PID: 1FC9:0143

USB Path: 0001:0008:00

Using memory from core 0 after searching for a good core

( 30) Emulator Connected

processor is in secure mode

debug interface type = CoreSight DP (DAP DP ID 6BA02477) over SWD TAP 0

processor type = Cortex-M33 (CPU ID 00000D21) on DAP AP 0

number of h/w breakpoints = 8

number of flash patches = 0

number of h/w watchpoints = 4

Probe(0): Connected&Reset. DpID: 6BA02477. CpuID: 00000D21. Info: <None>

Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled.

Content of CoreSight Debug ROM(s):

RBASE E00FE000: CID B105100D PID 0000095000 ROM (type 0x1)

ROM 1 E00FF000: CID B105100D PID 04000BB4C9 ROM (type 0x1)

ROM 2 E000E000: CID B105900D PID 04000BBD21 CSt ARM ARMv8-M type 0x0 Misc - Undefined

ROM 2 E0001000: CID B105900D PID 04000BBD21 CSt ARM DWTv2 type 0x0 Misc - Undefined

ROM 2 E0002000: CID B105900D PID 04000BBD21 CSt ARM FPBv2 type 0x0 Misc - Undefined

ROM 2 E0000000: CID B105900D PID 04000BBD21 CSt ARM ITMv2 type 0x43 Trace Source - Bus

ROM 2 E0041000: CID B105900D PID 04002BBD21 CSt ARM ETMv4.0 type 0x13 Trace Source - Core

ROM 2 E0042000: CID B105900D PID 04000BBD21 CSt ARM CTIv2 type 0x14 Debug Control - Trigger, e.g. ECT

ROM 1 E0040000: CID B105900D PID 04000BBD21 CSt type 0x11 Trace Sink - TPIU

ROM 1 E0044000: CID B105900D PID 04003BB908 CSt CSTF type 0x12 Trace Link - Trace funnel/router

ROM 1 E0045000: CID B105900D PID 04001BB961 CSt type 0x21 Trace Sink - ETB

NXP: MCXN947

DAP stride is 1024 bytes (256 words)

Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx

Image 'MCXN9xx_SFDP_FlexSPI Mar 6 2025 18:26:01'

Opening flash driver MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx

VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead.

Using SOFT reset to run the flash driver

Driver V.2 dynamic startup failed - driver Init provided no flash parameters

driver describes no sectors starting at 0x80000000

Flash Driver V.2 startup failed - rc Ef(58): Flash Driver describes no sectors at its base address

chip initialization failed - Ef(58): Flash Driver describes no sectors at its base address

failed to initialize flash driver MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx

Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx

Image 'MCXN9xx_SFDP_FlexSPI Mar 6 2025 18:26:01'

Opening flash driver MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx

VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead.

Using SOFT reset to run the flash driver

Driver V.2 dynamic startup failed - driver Init provided no flash parameters

driver describes no sectors starting at 0x80000000

Flash Driver V.2 startup failed - rc Ef(58): Flash Driver describes no sectors at its base address

chip initialization failed - Ef(58): Flash Driver describes no sectors at its base address

failed to initialize flash driver MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx

Is it necessary to change anything other than CONFIG_OPTION0 for MX25L3233F?

Best regards

[Harry_Zhang]

Hi @takagi_y 

On FRDM-MCXN947, the Qflash is W25Q64JVSSIQ.

On your customer board, the qflash is MX25L3233F.

So you need to change the Flash burning algorithm.

Such as MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx

And in the mcxn_flexspi_nor_config.c

Change the LUT

BR

Harry

[takagi_y]

Thank you for your reply.

I compared the data sheets for W25Q64JVSSIQ and MX25L3233F and confirmed that the LUT contents are the same.

> So you need to change the Flash burning algorithm.
> Such as MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx

Does the above mean that you need to change the code other than CONFIG_OPTION0 and CONFIG_OPTION1 in MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx?

Or does it mean that there are other files that need to be modified besides MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx?

If other files need to be modified, could you please let me know the files?

Best regards

[Harry_Zhang]

Hi @takagi_y 

Apart from MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx and mcxn_flexspi_nor_config.c, there are no other files that need to be modified.

"I compared the data sheets for W25Q64JVSSIQ and MX25L3233F and confirmed that the LUT contents are the same."

No, they are different.

You can refer to the flexspi_polling example, it includes the LUT of W25Q64JVSSIQ and MX25L3233F.

#if EXAMPLE_FLASH_TYPE == FLASH_W25Q64
/* W25Q64JVSSIQ */
const uint32_t customLUTOctalMode[CUSTOM_LUT_LENGTH] = {
    /* Read data */
    [4 * NOR_CMD_LUT_SEQ_IDX_READ] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xEB, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 0x18),
    [4 * NOR_CMD_LUT_SEQ_IDX_READ + 1] = FLEXSPI_LUT_SEQ(
        kFLEXSPI_Command_MODE8_SDR, kFLEXSPI_4PAD, 0xF0, kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x04),
    [4 * NOR_CMD_LUT_SEQ_IDX_READ + 2] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x00, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

    /* Read status register */
    [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x00),

    /* Write enable */
    [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

    /* Write enable */
    [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_OPI] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

    /* Read ID */
    [4 * NOR_CMD_LUT_SEQ_IDX_READID_OPI] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x9F, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x00),

    /* Sector erase */
    [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x20, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),

    /* Chip erase */
    [4 * NOR_CMD_LUT_SEQ_IDX_CHIPERASE] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x60, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

    /* Page program */
    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x32, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x00, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

    /* Enter Quad mode */
    [4 * NOR_CMD_LUT_SEQ_IDX_ENTEROPI] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x00),

    /*  Dummy write, do nothing when AHB write command is triggered. */
    [4 * NOR_CMD_LUT_SEQ_IDX_WRITE] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),

    /*  Read status register using Quad mode */
    [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x00),

};
#endif

#if EXAMPLE_FLASH_TYPE == FLASH_MT35XU512
/* MT35XU512ABA1G12 */
const uint32_t customLUTOctalMode[CUSTOM_LUT_LENGTH] = {

    /*  OPI DDR read */
    [4 * NOR_CMD_LUT_SEQ_IDX_READ] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xCC, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xCC),
    [4 * NOR_CMD_LUT_SEQ_IDX_READ + 1] = FLEXSPI_LUT_SEQ(
        kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x0D),
    [4 * NOR_CMD_LUT_SEQ_IDX_READ + 2] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

    /* Read status register */
    [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x00),

    /* Write Enable */
    [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

    /* Read ID under octal mode */
    [4 * NOR_CMD_LUT_SEQ_IDX_READID_OPI] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x9F, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x9F),
    [4 * NOR_CMD_LUT_SEQ_IDX_READID_OPI + 1] = FLEXSPI_LUT_SEQ(
        kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x00),

    /*  Write Enable */
    [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_OPI] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x06, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x06),

    /*  Erase Sector */
    [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20),
    [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR + 1] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

    /*  Erase Chip */
    [4 * NOR_CMD_LUT_SEQ_IDX_CHIPERASE] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x60, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x60),

    /*  Program */
    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x8E, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x8E),
    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1] = FLEXSPI_LUT_SEQ(
        kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x00),

    /* Enter OPI mode */
    [4 * NOR_CMD_LUT_SEQ_IDX_ENTEROPI] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x81, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
    [4 * NOR_CMD_LUT_SEQ_IDX_ENTEROPI + 1] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x00, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

    /*  Dummy write, do nothing when AHB write command is triggered. */
    [4 * NOR_CMD_LUT_SEQ_IDX_WRITE] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),

    /*  Read status register using Octal DDR read */
    [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
    [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI + 1] = FLEXSPI_LUT_SEQ(
        kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x00),
};
#endif

BR

Harry

[takagi_y]

Thank you for your reply.

I have checked the example you provided.
The Flash I want to use is MX25L3233F.
The example you provided is for MT35XU512ABA, which is a different model number.

The following is an excerpt of the MX25L3233F command, which is the same as the MT35XU512ABA command.

It is MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx, but do I need to make any changes other than to FlashConfig.h?

Best regards

[Harry_Zhang]

Hi @takagi_y 

Apart from MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx and  FlashConfig.h, there are no other files that need to be modified.

BR

Harry

[takagi_y]

Thank you for your reply.

I have only modified the two files you mentioned, but the error still occurs.

I will upload the files I am using and the error message.

I cannot identify the reason why the Flash Driver V2 fails to start, so please give me some advice.

mcxn_flexspi_nor_config.c
In this file, the value of sflashA1Size has been changed from 8M to 4M.

/*
* Copyright 2018-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/

#include "mcxn_flexspi_nor_config.h"

/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif

/*******************************************************************************
* Code
******************************************************************************/

#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".flexspi_fcb"), used))
#elif defined(__ICCARM__)
#pragma location = ".flexspi_fcb"
#endif

#ifndef FLEXSPI_USE_CUSTOM_FCB
#define FLEXSPI_USE_CUSTOM_FCB (0)
#endif

#if FLEXSPI_USE_CUSTOM_FCB
/* FCB for W25Q64 */
const uint8_t CUSTOM_FCB[] = {
0x46, 0x43, 0x46, 0x42, 0x00, 0x04, 0x01, 0x56, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xeb, 0x04, 0x18, 0x0a, 0x06,
0x32, 0x04, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x04, 0x04, 0x24, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
0x04, 0x18, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x04, 0x18, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0x18, 0x08, 0x04, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x60, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
#else

/* FCB for W25Q64 */
const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClksrc=kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 3u,
.csSetupTime = 3u,
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
.controllerMiscOption = (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable),
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_75MHz,
.sflashA1Size = 4u * 1024u * 1024u,
.lookupTable =
{
// Read LUTs
[0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
[1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),

// Read Status LUTs
[4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),

// Write Enable LUTs
[4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0),

// Erase Sector LUTs
[4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18),

// Erase Block LUTs
[4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18),

// Pape Program LUTs
[4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18),
[4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),

// Erase Chip LUTs
[4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.ipcmdSerialClkFreq = 1u,
.blockSize = 64u * 1024u,
.isUniformBlockSize = false,
};
#endif

FlashConfig.h
I created four different versions of this file with different values ​​for CONFIG_OPTION0. (0xC0000001, 0xC0000405, 0xC0000401, 0xC0000101)
I have used each one to check.

//*****************************************************************************
// FlashConfig.h
// MCUXpresso IDE Flash driver
// Config file for MCXN9xx FlexSPI driver
//*****************************************************************************
//
// Copyright 2022-2024 NXP
//
// SPDX-License-Identifier: BSD-3-Clause
//*****************************************************************************

#ifndef FLASHCONFIG_H_
#define FLASHCONFIG_H_

#include "fsl_flexspi_nor_flash.h"

extern flexspi_nor_config_t flashConfig;

#if defined (DEBUG)
#define MCXN9xx_SFDP_FlexSPI
#endif

// MCX N1xNxxx Reference Manual - 15.4.2 FlexSPI NOR Configuration Option Block

#if defined (MCXN9xx_SFDP_FlexSPI) || defined (MCXN9xx_SFDP_FlexSPI_S)
/*
* 0xC : tag
* 0 : option_size (0 = option1 not specified)
* 0 : device_type (0 = Read SFDP for SDR commands)
* 0 : query_pads (0 = 1 data pad during query)
* 0 : cmd_pads (0 = 1 data pad during flash access)
* 0 : quad_mode_setting (0 = not configured)
* 0 : misc_mode
* 1 : max_freq (0 = Don't change FlexSPI clock setting)
*/
#define CONFIG_OPTION0 0xC0000001
//#define CONFIG_OPTION0 0xC0000405
//#define CONFIG_OPTION0 0xC0000401
//#define CONFIG_OPTION0 0xC0000101

/*
* 0x0 : Single Flash connected to Port A
*/
#define CONFIG_OPTION1 0x00000000

#endif

// =====================================
// Flash Base Address Information
// =====================================
#if defined (MCXN9xx_SFDP_FlexSPI_S)
#define USE_SECURE_FLASHADDR
#define FLASH_BASE_ADDR 0x90000000
#else
#define FLASH_BASE_ADDR 0x80000000
#endif

#endif /* FLASHCONFIG_H_ */

When 0xC0000001 is used for CONFIG_OPTION0, the following Console A is displayed on the Console, and when not, Console B is displayed.

Console A

MCUXpresso IDE RedlinkMulti Driver v24.9 (Sep 19 2024 19:34:05 - crt_emu_cm_redlink build 802)
Found chip XML file in C:/WorkSpace/MCUX/MCUXpressoIDE_24.9.25/NX-N947/NX-N947_ledblinky/frdmmcxn947_led_blinky/Debug_NoRAM\MCXN947.xml
( 5) Remote configuration complete
Reconnected to existing LinkServer process.
Probe Firmware: MCU-LINK (r0FF) CMSIS-DAP V3.153 (NXP Semiconductors)
Serial Number: VUDADS0NIE0ZM
VID:PID: 1FC9:0143
USB Path: 0001:0003:00
Using memory from core 0 after searching for a good core
processor is in secure mode
debug interface type = CoreSight DP (DAP DP ID 6BA02477) over SWD TAP 0
processor type = Cortex-M33 (CPU ID 00000D21) on DAP AP 0
number of h/w breakpoints = 8
number of flash patches = 0
number of h/w watchpoints = 4
Probe(0): Connected&Reset. DpID: 6BA02477. CpuID: 00000D21. Info: <None>
Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled.
Content of CoreSight Debug ROM(s):
RBASE E00FE000: CID B105100D PID 0000095000 ROM (type 0x1)
ROM 1 E00FF000: CID B105100D PID 04000BB4C9 ROM (type 0x1)
ROM 2 E000E000: CID B105900D PID 04000BBD21 CSt ARM ARMv8-M type 0x0 Misc - Undefined
ROM 2 E0001000: CID B105900D PID 04000BBD21 CSt ARM DWTv2 type 0x0 Misc - Undefined
ROM 2 E0002000: CID B105900D PID 04000BBD21 CSt ARM FPBv2 type 0x0 Misc - Undefined
ROM 2 E0000000: CID B105900D PID 04000BBD21 CSt ARM ITMv2 type 0x43 Trace Source - Bus
ROM 2 E0041000: CID B105900D PID 04002BBD21 CSt ARM ETMv4.0 type 0x13 Trace Source - Core
ROM 2 E0042000: CID B105900D PID 04000BBD21 CSt ARM CTIv2 type 0x14 Debug Control - Trigger, e.g. ECT
ROM 1 E0040000: CID B105900D PID 04000BBD21 CSt type 0x11 Trace Sink - TPIU
ROM 1 E0044000: CID B105900D PID 04003BB908 CSt CSTF type 0x12 Trace Link - Trace funnel/router
ROM 1 E0045000: CID B105900D PID 04001BB961 CSt type 0x21 Trace Sink - ETB
NXP: MCXN947
DAP stride is 1024 bytes (256 words)
Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MCXN9xx_SFDP_FlexSPI_0xC0000001.cfx
Image 'MCXN9xx_SFDP_FlexSPI Mar 21 2025 14:26:16'
Opening flash driver MCXN9xx_SFDP_FlexSPI_0xC0000001.cfx
VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead.
Using SOFT reset to run the flash driver
Flash variant 'JEDEC_FlexSPI_Device' detected (0B = at 0x80000000)
driver describes no sectors starting at 0x80000000
Flash Driver V.2 startup failed - rc Ef(58): Flash Driver describes no sectors at its base address
chip initialization failed - Ef(58): Flash Driver describes no sectors at its base address
failed to initialize flash driver MCXN9xx_SFDP_FlexSPI_0xC0000001.cfx
Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MCXN9xx_SFDP_FlexSPI_0xC0000001.cfx
Image 'MCXN9xx_SFDP_FlexSPI Mar 21 2025 14:26:16'
Opening flash driver MCXN9xx_SFDP_FlexSPI_0xC0000001.cfx
VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead.
Using SOFT reset to run the flash driver
Flash variant 'JEDEC_FlexSPI_Device' detected (4MB = 64*64K at 0x80000000)
Closing flash driver MCXN9xx_SFDP_FlexSPI_0xC0000001.cfx

Console B

MCUXpresso IDE RedlinkMulti Driver v24.9 (Sep 19 2024 19:34:05 - crt_emu_cm_redlink build 802)
Found chip XML file in C:/WorkSpace/MCUX/MCUXpressoIDE_24.9.25/NX-N947/NX-N947_ledblinky/frdmmcxn947_led_blinky/Debug_NoRAM\MCXN947.xml
( 5) Remote configuration complete
Reconnected to existing LinkServer process.
Probe Firmware: MCU-LINK (r0FF) CMSIS-DAP V3.153 (NXP Semiconductors)
Serial Number: VUDADS0NIE0ZM
VID:PID: 1FC9:0143
USB Path: 0001:0003:00
Using memory from core 0 after searching for a good core
processor is in secure mode
debug interface type = CoreSight DP (DAP DP ID 6BA02477) over SWD TAP 0
processor type = Cortex-M33 (CPU ID 00000D21) on DAP AP 0
number of h/w breakpoints = 8
number of flash patches = 0
number of h/w watchpoints = 4
Probe(0): Connected&Reset. DpID: 6BA02477. CpuID: 00000D21. Info: <None>
Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled.
Content of CoreSight Debug ROM(s):
RBASE E00FE000: CID B105100D PID 0000095000 ROM (type 0x1)
ROM 1 E00FF000: CID B105100D PID 04000BB4C9 ROM (type 0x1)
ROM 2 E000E000: CID B105900D PID 04000BBD21 CSt ARM ARMv8-M type 0x0 Misc - Undefined
ROM 2 E0001000: CID B105900D PID 04000BBD21 CSt ARM DWTv2 type 0x0 Misc - Undefined
ROM 2 E0002000: CID B105900D PID 04000BBD21 CSt ARM FPBv2 type 0x0 Misc - Undefined
ROM 2 E0000000: CID B105900D PID 04000BBD21 CSt ARM ITMv2 type 0x43 Trace Source - Bus
ROM 2 E0041000: CID B105900D PID 04002BBD21 CSt ARM ETMv4.0 type 0x13 Trace Source - Core
ROM 2 E0042000: CID B105900D PID 04000BBD21 CSt ARM CTIv2 type 0x14 Debug Control - Trigger, e.g. ECT
ROM 1 E0040000: CID B105900D PID 04000BBD21 CSt type 0x11 Trace Sink - TPIU
ROM 1 E0044000: CID B105900D PID 04003BB908 CSt CSTF type 0x12 Trace Link - Trace funnel/router
ROM 1 E0045000: CID B105900D PID 04001BB961 CSt type 0x21 Trace Sink - ETB
NXP: MCXN947
DAP stride is 1024 bytes (256 words)
Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx
Image 'MCXN9xx_SFDP_FlexSPI Mar 6 2025 18:26:01'
Opening flash driver MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx
VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead.
Using SOFT reset to run the flash driver
Driver V.2 dynamic startup failed - driver Init provided no flash parameters
driver describes no sectors starting at 0x80000000
Flash Driver V.2 startup failed - rc Ef(58): Flash Driver describes no sectors at its base address
chip initialization failed - Ef(58): Flash Driver describes no sectors at its base address
failed to initialize flash driver MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx
Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx
Image 'MCXN9xx_SFDP_FlexSPI Mar 6 2025 18:26:01'
Opening flash driver MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx
VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead.
Using SOFT reset to run the flash driver
Driver V.2 dynamic startup failed - driver Init provided no flash parameters
driver describes no sectors starting at 0x80000000
Flash Driver V.2 startup failed - rc Ef(58): Flash Driver describes no sectors at its base address
chip initialization failed - Ef(58): Flash Driver describes no sectors at its base address
failed to initialize flash driver MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx

Best regards

[Harry_Zhang]

Hi @takagi_y 

Have we considered hardware connectivity issues?

Are you a custom board？

If you are a custom board, can you connect this flash to FRDM-MXN947?

And try again.

If the flash still cannot work when connected to FRDM-MXN947.

I will buy this flash and test it.

BR

Harry

[takagi_y]

Thank you for your reply.

As you suggested, I replaced the Flash of FRDM-MXN947 with MX25L3233 and checked.
I was able to write when I used the same mcxn_flexspi_nor_config.c as the one I uploaded the other day and FlashConfig.h with CONFIG_OPTION0 set to 0xC0000101.

However, I cannot write on my board even when I use the same file.

On my board, I use port A in INDIVIDUAL mode, so SS0_b is connected to MX25L3233 and SS1_b is connected to PSRAM, but I wonder if PSRAM is affecting it.
I have attached a circuit diagram showing the connection of Flash and PSRAM.
If you have any comments, please give me some advice.

 

Also, I have set the Memory configuration editor as follows.
The flash size is set to 0xffff000, but since I'm using a 4MByte product, I think 0x3ff000 is correct.
Will this size setting affect flash writing?

Best regards

[takagi_y]

We have confirmed the following regarding this issue and would like to inform you of the issue.

We suspected that the PSRAM may be affecting the circuit, so we opened JP1 in the circuit diagram uploaded yesterday and checked with the PSRAM electrically disconnected, but we were unable to write to the Flash.

If you have any advice, including about yesterday's post, we would appreciate it.

Best regards

[Harry_Zhang]

Hi @takagi_y 

"As you suggested, I replaced the Flash of FRDM-MXN947 with MX25L3233 and checked.
I was able to write when I used the same mcxn_flexspi_nor_config.c as the one I uploaded the other day and FlashConfig.h with CONFIG_OPTION0 set to 0xC0000101."

This proves that your software configuration is fine.

So I think it's still a hardware issue.

Can you try connecting to Nor Flash only?

Disconnect the PSRAM related electrically(including DATA CLOCK CS).

BR

Harry

[takagi_y]

Thank you for your reply.

Since the CEn of the PSRAM is fixed at the H level, I believe that the DATA and CLOCK of the PSRAM do not affect the QSPI Flash.

Are there any other possible causes?

Best regards

[takagi_y]

I have an additional question.

The PSRAM is electrically isolated, and in this state, writing can be done from the SEC tool.
If writing is done from the IDE in the same state, it fails.
If the PSRAM is affecting it, I think writing cannot be done with the SEC tool either.
What do you think?

Best regards

[Harry_Zhang]

Hi @takagi_y 

Yes, your analysis is correct.

If writing can be done from the SEC tool.

This proves that there is no issue with the hardware.

Previously, you verified that your software had no issues with FRDM mcxn947, and now you have verified that your hardware has no issues with SEC tool,

so can you work now?

BR

Harry

[takagi_y]

Thank you for your reply.

I can write from the SEC tool, but I cannot write from MCUXpresso IDE.

I think there is some reason why I cannot write from MCUXpresso IDE, but I don't know what it is.
Could you give me some advice?

Best regards

[Harry_Zhang · Accepted solution]

Hi @takagi_y 

You can write from the SEC tool, this proves that the FCB produced by SEC is correct.

So i think you can flash the correct FCB to 0x80000400.

And then delete mcxn_flexspi_nor_config.c and mcxn_flexspi_nor_config.h in MCUXpresso.

Because they generate the NEW FCB and flash in 0x80000400.

And you can debug it.

I tested, i generate the FCB.bin through the SEC tool. and flash it into 0x80000400.

And i can debug it successfully.

To summarize, put the correct FCB into 0x80000400, and put the correct application into 0x80001000.

BR

Harry

[takagi_y]

In this thread, I have asked a question about not being able to write using write_image_win.bat, but this has not yet been resolved.

I would like to summarize the current situation.

- When writing to a brand new board using a bat file, the process that should say "Erase memory before writing image" is displayed as "failed."

- Boards that have already been written to using the SEC tool can be written to using the bat file.

The following are the questions I would like to ask.

1. Why can't I write to a brand new board using a bat file?

2. Is there anything I need to do to write to a brand new board using a bat file?

3. Is there a difference between a board that has already been written to using the SEC tool and a brand new board?

Please answer.

Best regards

[Harry_Zhang]

Hi @takagi_y 

We have already resolved the previous issue. For this question, I suggest you create a new one in the community.

We will do our best to support you. Thank you for your understanding.

BR

Harry

[takagi_y]

Thank you for your reply.

Understood.
I have posted the question below, so please reply there.

https://community.nxp.com/t5/MCX-Microcontrollers/Writing-to-the-QSPI-Flash-of-MCXN947-using-write-i... 

Best regards