Where can I find the IOMUXC mux register address and SION bit settings for a specific pin ?

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Where can I find the IOMUXC mux register address and SION bit settings for a specific pin ?

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Manjunathb
Contributor II

I'm trying to check the current mux mode and SION bit value for a specific pin on i.MX9353. Where can I find the full list of IOMUXC SW_MUX_CTL_PAD registers and their bit fields (especially the SION bit)? Also, how can I identify the address for a pin like

IOMUXC_PAD_GPIO_IO12__TPM3_CH2

?

 

IMX93QSB i.MX93 SPIFI-NXP-MICROCONTROLLERS 

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Zhiming_Liu
NXP TechSupport
NXP TechSupport

Hi @Manjunathb 

The mux register is SW_MUX_CTL_PAD_GPIO_IO12, the naming rule is SW_MUX_CTL_PAD_ + PAD name, here GPIO_IO12 is PAD name. For drive strength, it's SW_PAD_CTL_PAD_ + PAD name.


Best Regards,
Zhiming

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Manjunathb
Contributor II

@Zhiming_Liu 

I'm using the MCUXpresso SDK for the i.MX93 Cortex-M33 MCU and working with GPIO input capture. The SDK-generated pin_mux.c file uses the IOMUXC_SetPinMux() API, which includes the inputOnfield parameter that controls the SION bit (Software Input On).

I understand that SION forces the input path to be always active, but I'm not sure:

  • What value should I pass for inputOnfield when using a pin as GPIO input only?

  • Is it safe to always set inputOnfield = 1, or could this cause issues in power or logic behavior?

  • How does this affect dual-use pins (e.g., GPIO + PWM or GPIO + UART)?

Could someone clarify the recommended practice for setting this field?

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Zhiming_Liu
NXP TechSupport
NXP TechSupport

Hi @Manjunathb 

For Q1 and Q2, GPIO input capture need to set iomux to GPIO mode and set the SION bit.

For Q3, what does dual-use mean? The iomux mode should be one state.

Best Regards,
Zhiming

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