Using USB on Core 1 of LPC55S6X (Zephyr OS)

alexfeinman · ‎02-08-2026

I am trying to figure out what needs to be done to assign a USB peripheral (device controller) to the CPU1 of LPC55S69 (LPCXPRESSO board)

I am building a modified cdc-acm sample project. The main core (CPU0) is flashed with a build that enabled CPU1. I have no issues running code on CPU1. I can for example handle button presses. But USB hardware does not initialize correctly. For example I see that inside USB_EhciPhyInit all writes to usbPhyBase->CTRL do not change its value from 0 (I am using Ozone debugger to look at the hardware registers).

To summarize - it looks like both USBPHY and USBHSD register ignore writes from the driver.

Things I've checked:

1. Same project works on CPU0
2. USB controllers and USB RAM are disabled in the CPU0 project I use to initialize and start CPU1
3. USB controllers and USB RAM are enabled on CPU1

Basically I hit the same SW path through the USB initialization as on CPU0 except the peripherals seem to be dead - as if the clock was not enabled

I am trying to figure out what needs to be done to assign a USB peripheral (device controller) to the CPU1 of LPC55S69 (LPCXPRESSO board)I am building a modified cdc-acm sample project. The main core (CPU0) is flashed with a build that enabled CPU1. I have no issues running code on CPU1. I can for example handle button presses. But USB hardware does not initialize correctly. For example I see that inside USB_EhciPhyInit all writes to usbPhyBase->CTRL do not change its value from 0 (I am using Ozone debugger to look at the hardware registers).To summarize - it looks like both USBPHY and USBHSD register ignore writes from the driver.Things I've checked:1. Same project works on CPU02. USB controllers and USB RAM are disabled in the CPU0 project I use to initialize and start CPU13. USB controllers and USB RAM are enabled on CPU1Basically I hit the same SW path through the USB initialization as on CPU0 except the peripherals seem to be dead - as if the clock was not enabled

Harry_Zhang · ‎02-10-2026

Hi @alexfeinman

On LPC55S69 the two M33 cores share the same peripherals, but CPU1 has no TrustZone, and by default many peripherals come up as Secure‑only.

LPCXPRESSO55S69 — Zephyr Project Documentation

BR

Harry

alexfeinman · ‎02-12-2026

Thank you. If I understand your reply correctly, my choice is to either use non-secure build on CPU0 or to configure trust zone to allow CPU1 USB access somehow. Could you point me to any resources on how to achieve the latter in Zephyr?

Harry_Zhang · ‎02-24-2026

Hi @alexfeinman

CPU1 (the second Cortex‑M33 in LPC55S69) does NOT support TrustZone at all.

You cannot "configure TrustZone to allow CPU1 USB access" in Zephyr.

May i ask what is your goal?

only USB device running on CPU1?

BR

Harry

alexfeinman · ‎03-24-2026

Apologies for late reply. Somehow notification emails ended up in junk folder.

My goal is to have the code handling the USB interface running on core 1, while core 0 is doing something unrelated. Essentially I want to use core 1 as a dedicated communication processor running multiple UART to USB bridges (4 total).