Resets from unknown sources MCXN947

[robert_hines]

I have a device with an MCXN947.  It's running FreeRTOS.  Using LPTMR, it periodically goes into power-down mode, wakes up on the timer interrupt, maybe does a few things, then goes back into power-down mode.  Something like this:

        vTaskSuspendAll();      // FreeRTOS

        PM_EnterLowPower(); // LPTMR interrupt will wake us up

        xTaskResumeAll();       // FreeRTOS

There's really only one other task running when it wakes up and it does some I2C comms.

The problem is that the processor occasionally resets (can't reliably reproduce).  The CMC SRS register reads 0x00004010, a warm SW reset.  Code isn't calling reset anywhere, maybe NXP's assert() or FreeRTOS's configASSERT().

Are there other internal sources could be causing a SW reset?

[robert_hines]

The SSRS register reads 0x00004430, so the RSTACK bit is set; could ERR051704 cause that?

[Alice_Yang]

Hello @robert_hines 

Yes, it is very likely related.

Please first refer to ERR051704 and ERR051993 for verification.

Alice_Yang_0-1789719190798.png

Also, SSRS contains cumulative status information, so it should be analyzed together with the current SRS value.

Thank you.

BR

Alice

[robert_hines]

Changing the active voltage to midvoltage (and high drive strength) and the low-power voltage to overdrive (and low drive strength) while dropping in and out of power-down mode once a second, did increase the number of resets, all of the form:

SRS 0x00004010
SSRS 0x00004430

It would be nice if NXP could describe the downstream effects of the errata so I could be more confident this is the source of these spurious resets.

[robert_hines]

Would this errata (MCXN_1P02G) cause resets?

ERR051704 DCDC: Failure changing to Low drive-strength mode