MCXN547VNLT power on reset problem

[plac]

I am debugging a proprietary board based on MCXN547VNLT.

During the MCU power-up sequence, I do not see the “kCMC_PORReset” flag in the SRS register.
So I inspected the MCU reset signal and saw two resets on the pin (see attached oscillogram: blue signal is the pin Reset and yellow signal is the VCC).

Has anyone else seen and resolved a similar issue?
This issue prevents me from detecting the first power-up of the MCU in my application.

[Habib_MS]

Hello @plac,
In order to try a pinpoint if the issue is related to hardware, could you please confirm that your design follows the required sequence mentioned in the chapter 2.5 in the datasheet ? 

please verify if the 100 nF capacitor mentioned in the “HMI Interfaces” section of the UG10092: MCXNx4x Hardware Design Guide | NXP Semiconductors is properly included.

BR
Habib

[plac]

Thank you for your help.

In our design, the VDD_P2, VDD_P4, VDD_ANA, and VDD_BAT pins are connected to VDD. VDD_P3 is left floating (port P3 is not used).

VDD_CORE rises well after VDD (see attached oscillogram: channel 2 = MCU_RESET_B pin, channel 1 = VDD, channel 3 = VDD_CORE).

On the reset pin, we have a capacitance of 100nf and a resistance of 10K (the 100 Ohm resistor R193 and switch SW1 are not present).

[Habib_MS]

Hello @plac,
The reason the MCU_RESET_B behaves this way is that during reset, the RESET_b drives low until the MCU completes initialization, at which point the RESET_b pin is released. If the RESET_b pin asserts externally, then the MCU remains in reset until the RESET_b input is pulled high. As mentioned in the chapter 38.3.5.1 called "Reset sources" in the RM.
In order to support you better, could you provide me the following information?
-The code you are using to read the CMC register and the value it returns.
- Previously, were you able to observe the SRS[POR] bit? If so, could you share the changes you made in either software or hardware?

BR
Habib

[plac]

Hello,
The RESET_b pin is not controlled externally except when VDD is applied by the RC network. If you look at the oscillogram provided in my previous reply, you can see that the RESET_b pin is forced low by the ROM code.
I just ran a test by invalidating the CMPA region parameters. To do this, I cleared the BOOT_CFG [HEADER] register. By doing this, I no longer have the double reset and I can see that the SRS[POR] bit is set to 1.
So I assume that the CMPA region configuration is not correct? Do you have an explanation for this problem?
Thank you.

[plac]

I just read through the Security Reference Manual, and I noticed that the CMPA[FLASH_REMAP_SIZE] field is not set to zero. When I set this field to zero, I no longer get this double reset. Can you explain why? The answer is not clear in the SRM document in chapter 8.3.1.1.1 Boot flow.

[Habib_MS · Accepted solution]

Hello @plac,
The CMPA is designed to control certain boot behaviors, and misconfiguration can lead to unexpected resets during the boot flow. It’s possible that the issue you observed was related to an error in the boot sequence that caused the MCU to reset differently.

To prevent this from happening, you can overwrite the CMPA with your own configurations (which, as I understand, you already did). You can find more detailed information in Chapter 8.5: Customer Manufacturing/Factory Programmable Area (CMPA) of the Security Reference Manual.
BR
Habib