MCXN547 SC Timer0 SDK driver Issue

[JawaharA]

I am using MCXN547VKL MCU and SDK version 26.06.00. 

Context: I am using SCT timer0  to generate two different PWM waveform using the COUNTER in split mode, CONFIG[UNIFY] = 0; i.e COUNT_L for one PWM generator and COUNT_H for another PWM generator.

The issue: When I load the COUNTER_H with the driver API "SCTIMER_SetCOUNTValue(SCT0,kSCTIMER_Counter_H,0U);" , Bus Fault occurs. 

I traced the issue to SDK driver code. The driver code uses 32 bit write to write both COUNT_H and COUNT_L instead of 16 bit write to COUNT_H alone. While the COUNT_H is being written COUNT_L was running and this caused bus fault. I modified the SDK driver code to use 16 bit write and the bus fault did not occur. I have attached the driver code and marked with colours, the code line which was causing the problem and the fix. If this is really the problem, the SDK driver can be updated. - Thanks

/*!

* @brief Set the value of counter.

*

* The function is to set the value of Count register, Writing to the COUNT_L, COUNT_H, or unified register

* is only allowed when the corresponding counter is halted (HALT bits are set to 1 in the CTRL register).

*

* @param base SCTimer peripheral base address

* @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H,

* In 32-bit mode, we can select Counter_U.

* @param value the counter value update to the COUNT register.

*/

static inline void SCTIMER_SetCOUNTValue(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t value)

{

SCTIMER_StopTimer(base, (uint32_t)whichCounter);

switch (whichCounter)

{

case kSCTIMER_Counter_L:

assert(value <= 0xFFFFU);

assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK));

/* Use Counter_L bits when user wants to setup the Low counter */

base->COUNT_ACCESS16BIT.COUNTL = (uint16_t)value;

break;

case kSCTIMER_Counter_H:

assert(value <= 0xFFFFU);

assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK));

/* Use Counter_H bits when user wants to setup the High counter */

// base->COUNT = (uint32_t)base->COUNT_ACCESS16BIT.COUNTL | SCT_COUNT_CTR_H(value);

base->COUNT_ACCESS16BIT.COUNTH = (uint16_t)value; //the fix

break;

case kSCTIMER_Counter_U:

assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK));

/* Use both Counter_L/Counter_H bits when counter is operating in 32-bit mode (unify counter). */

base->COUNT = value;

break;

default:

/* Fix the MISRA C-2012 issue rule 16.4. */

break;

}

SCTIMER_StartTimer(base, (uint32_t)whichCounter);

}

[Harry_Zhang]

Hi @JawaharA 

Thank you for your feedback. Your analysis of the cause of the Bus Fault is correct: updating COUNT_H uses a 32-bit write to the COUNT register, but the current function halts only the H counter. If the L counter is still running, this write access triggers an SCT bus error.

However, changing the access to a 16-bit write to COUNTH is not compliant with the SCT hardware access requirements, because COUNT_H must be written as a word together with COUNT_L . The correct software solution is to halt both the L and H counters before performing the 32-bit write to COUNT , and then restore their previous running states afterward. We recommend reviewing and updating the SDK accordingly rather than using a separate 16-bit write to COUNT_H .

BR

Harry