The Cortex-M33 core is not actually documented in the reference manual for the MCX-A346, I assume since we can refer to ARM's corresponding technical ref manual. Fair enough. However, the state of the core as encountered when my program gets control (initial PC value at address 0x4) is different from what is defined as reset state in ARM's manual. Assuming that the core hardware is implemented according to the specs, I suppose it's the boot ROM code that leaves behind the non-conforming state [1].
Is this initial core state documented, and if yes, where? Thanks.
[1] Examples:
1) PRIMASK = 1
2) The FPU is enabled, but worse, CONTROL.FPCA = 1, ie. indicating the use of FPU instructions before my code runs. Now every exception in thread mode is tainted by this flag, resulting in an extended stack frame including the FPU registers even if my code does not use any FPU instructions, which wastes stack memory (thanks to lazy stacking the run-time overhead is minimal).
Of course, both of these issues can be resolved in my initialisation code. It would just be helpful to have this, and possibly other such cases I have yet to "discover", documented.
