// ====== FLEXPWM2 Setup: PWM2_0_A on Pin 4 slave======
// Enable clock for FLEXPWM2 (CG9: bits 19-18)
CCM_CCGR4 |= (3 << 18); // FLEXPWM2 for Pin 4 (PWM2_0_A)
// Set pin 4 to ALT1 = FLEXPWM2_PWM0_A
CORE_PIN4_CONFIG = 1;
FLEXPWM2_MCTRL &= ~(FLEXPWM_MCTRL_RUN(1 << 0)); //stop it at the begining
FLEXPWM2_SM0CTRL2 = FLEXPWM_SMCTRL2_INDEP|FLEXPWM_SMCTRL2_INIT_SEL(3); //independent + init select = EXT_SYNC
FLEXPWM2_SM0CTRL = FLEXPWM_SMCTRL_PRSC(0) | FLEXPWM_SMCTRL_FULL;
FLEXPWM2_SM0INIT = 0;
FLEXPWM2_SM0VAL0 = 0;
FLEXPWM2_SM0VAL1 = 0;
FLEXPWM2_SM0VAL2 = 0+PHASE;
FLEXPWM2_SM0VAL3 = (DUTY+PHASE);
FLEXPWM2_OUTEN |= FLEXPWM_OUTEN_PWMA_EN(1 << 0);
FLEXPWM2_MCTRL |= FLEXPWM_MCTRL_LDOK(1 << 0);
FLEXPWM2_MCTRL |= FLEXPWM_MCTRL_RUN(1 << 0);
//FLEXPWM3_PWM1 MASTER
uint32_t freq_kHz = 500;
// Enable clock for FLEXPWM3 (CG9: bits 20-21)
CCM_CCGR4 |= (3 << 20);
//enable clock for xbar1
CCM_CCGR2 |= CCM_CCGR2_XBAR1(CCM_CCGR_ON);
// VAL1 determines frequency
uint32_t M = IPG_CLOCK_HZ / (freq_kHz * 1000);
// Configure PWM3 SM1 as EXT_SYNC generator
FLEXPWM3_MCTRL &= ~(FLEXPWM_MCTRL_RUN(1 << 1));
FLEXPWM3_SM1CTRL2 = FLEXPWM_SMCTRL2_INDEP;
FLEXPWM3_SM1CTRL = FLEXPWM_SMCTRL_PRSC(0) | FLEXPWM_SMCTRL_FULL;
FLEXPWM3_SM1INIT = 0;
FLEXPWM3_SM1VAL0 = 0;
FLEXPWM3_SM1VAL1 = M;
FLEXPWM3_SM1VAL2 = 0;
FLEXPWM3_SM1VAL3 = M/2;
FLEXPWM3_SM1VAL5 = M/2;
// Enable OUT_TRIG1 on VAL1 match
FLEXPWM3_SM1TCTRL = (uint16_t)(1 << 1); // OUT_TRIG_EN bit 1 = PWM_OUT_TRIG1 on VAL1 match
// Route FLEXPWM3_SM1_OUT_TRIG1:XBAR1_IN48 → XBARA1_OUT_FLEXPWM2_PWM0_EXT_SYNC 44
XBARA1_SEL22 &= 0xff00; //Clear the SEL44 fields
XBARA1_SEL22 |= 48; ///
FLEXPWM3_OUTEN |= FLEXPWM_OUTEN_PWMB_EN(1 << 1);
FLEXPWM3_MCTRL |= FLEXPWM_MCTRL_LDOK(1 << 1);
FLEXPWM3_MCTRL |= FLEXPWM_MCTRL_RUN(1 << 1);