2S TDM Master: Persistent 1-slot downward shift during continuous DMA streaming

[Xanderwangx]

1. Test Configuration

• I2S configured as TDM Master, DSP mode with short WS
• 8 slots per frame, 32-bit per slot, frame length = 256 bit
• Using fsl_i2s_dma driver
• Dual-buffer ping-pong transfer
• FreeRTOS task waits on a semaphore from the DMA callback, fills the buffer, then calls I2S_TxTransferSendDMA to re-submit
• Test data pattern: fixed 0x000Axxxx (upper 16 bits = 0x000A, lower 16 bits contain slot index and sample sequence number)

2. Persistent One-Slot Downward Shift (100% Reproducible)

Logic analyzer captures show:

• Transmitted data is consistently shifted down by exactly one slot
• Data intended for Slot 0 appears in the physical Slot 1 position
• Data intended for Slot 1 appears in the physical Slot 2 position
• By extension, data intended for Slot 7 appears in Slot 0 of the next frame (or is lost)
• This shift is stable after the stream starts; it does not drift further over time and remains a fixed 1-slot offset

3. Startup Data Misalignment (Intermittent)

The logic analyzer occasionally observes:

• After the WS frame sync pulse, the DATA line remains at low level (all zeros) for a period
• After a blank interval of 1~3 frames, valid test data suddenly appears
• Once the blank interval ends, the data still exhibits the 1-slot offset described in item 2
  

[Celeste_Liu]

Hello @Xanderwangx ,

Thank you for your post. Could you please let us know which NXP MCU you are using? Also, are you working with one of our evaluation boards or a custom board? Are you using the SDK example code, or is this based on your own implementation? If it is your own code, would you be able to share it with us for further analysis?

BR

Celeste