SDK SPI driver performance

[scottm]

I decided to give the MCUX SDK SPI driver for the LPC55S69 before jumping into writing my own, which is always a bit of a pain. The performance in interrupt mode is pretty meager - with a SPI clock rate of 50 MHz I'm getting about 800 KB/sec throughput. The dead time between bytes is over 1 us.

Obviously this is going to need to use DMA to get anywhere close to its theoretical performance. The FreeRTOS-compatible driver provided with the SDK only supports interrupt mode, though.

Before I start trying to wrap the DMA driver to make it usable with FreeRTOS, is it even worth doing? How much overhead does the driver have? The problem I always have with the vendor-provided drivers is that for NOR flash setup the overhead involved in setting up the transfers (which include the command and address bytes) kills the throughput. I've seen it take as long to do the address setup as it does to transfer a 512-byte LBA.

Is there an efficient implementation geared toward SPI NOR flash? Or should I just suck it up, learn the LPC DMA controller, and port my own driver from Kinetis?

Thanks,

Scott

[xiangjun_rong]

Hi,

For the spi module, if you use spi clock with 50MHz, in theory, the spi byte throughput is 50MHz/8=6MByte/s. But you can get 0.8MByts/s actually now.

If you want to get maximum throughput, I suppose that you can use 16 bits half-word width when you transfers each times, secondly, the SPI module supports 8 entries of 16 bits FIFO, you can enable the FIFO mode, when the empty bit FIFOSTAT[TXEMPTY] is set, an interrupt is fired, in the ISR, you can check the FIFOSTAT[TXLVL] to know the FIFO actual empty size, then write multiple data from memory to the FIFO until the FIFO is filled fully in one ISR, of course, using FIFO can increase the efficiency.

The SPI supports DMA mode, you can use DMA to transfer data from memory to the SPI data register. We have the DMA plus SPI example in SDK package.

Hope it can help you

BR

XiangJun Rong

[scottm]

Hi,

I'm specifically asking about the performance of the driver provided with the SDK. Can the driver be configured to make efficient use of the FIFO?

And my question about the DMA performance relates to the transaction overhead rather than the throughput. To set up a read from a SPI NOR flash memory you've got to send a read command and the address and then perform the read. Are there any examples of the SDK being used for efficient flash access?

I wrote my own highly-optimized driver for the Kinetis family that does 16-bit words to squeeze a few percent more performance and that keeps the transaction overhead low, but again I'm trying to avoid having to rewrite all of that for LPC when it's a fairly common use case.

Thanks,

Scott

[xiangjun_rong]

Hi,

The SPI driver is inefficient, if you want to get the spi fastest transfer, I suggest you use polling mode and directly write the spi FIFOWR register, poll the status register and check if the transfer is over....

Hope it can help you

BR

XiangJun Rong