RW612 FLEXCOMM3/I2S3 Supporting driver

[duyhung]

We are using RW612 FLEXCOMM3/I2S3 with the following fixed hardware wiring:

- GPIO24 = I2S DATA input from PCM6120 SDOUT
- GPIO25 = I2S SCK output to PCM6120 BCLK
- GPIO26 = I2S WS output to PCM6120 FSYNC

The codec is PCM6120 in slave mode.
RW612 is intended to be the I2S master generating BCLK/WS and receiving audio data.

What we have verified:
- GPIO25/GPIO26 can be driven correctly in plain GPIO mode
- FLEXCOMM3 clock source is AUDIO PLL at 12.288 MHz
- I2C communication with PCM6120 is working
- PCM6120 register configuration is accepted

Observed behavior:
1. FLEXCOMM3 configured as I2S RX with kI2S_MasterSlaveNormalMaster does not generate any SCK/WS edges on GPIO25/GPIO26.
2. FLEXCOMM3 configured as I2S TX with kI2S_MasterSlaveNormalMaster also does not work: FIFOSTAT.TXNOTFULL=1, but TXLVL remains 0 after writes to FIFOWR, and no SCK/WS edges appear on the pins.
3. PCM6120 reports missing clocks (ASI_STS=0xFF, DEV_STS1=0x80).

Questions:
1. Is RW612 FLEXCOMM I2S RX in Normal Master mode expected to drive SCK/WS onto external pins?
2. Is a single FLEXCOMM instance supported for the use case “master clock generation + receive data from external codec”, or is a dual-FLEXCOMM architecture (TX master + RX slave with I2S bridge) required?
3. For FLEXCOMM3 I2S TX master, are there additional prerequisites for FIFO writes to be accepted beyond I2S_TxInit(), FIFOWR writes, and MAINENABLE?
4. Is there any known limitation specific to FLEXCOMM3 on GPIO24/25/26 (AON domain) for I2S clock output?

Pls help about the topic

[RomanVR]

Hi @duyhung, hope you are doing well.

Would you please clarify if you are using FreeRTOS or Zephyr to perform the tests? Are you using the FRDM-RW612 board?

Please also provide which version (either SDK or Zephyr) you are using, and if you're taking an example as base for your development.

Additionally, the Reference Manual of RW612 (UM11865) includes a basic configuration guide for I2S peripheral in section 28.2, would you please confirm if you have followed this general steps?

[duyhung]

Hi @RomanVR ,

Thank you for your response. Please find the clarifications below.

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1. RTOS

We are using bare-metal and FreeRTOS for both test. No Zephyr is involved in these tests. All initialization and I2S configuration are done directly with the NXP SDK drivers.

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2. Board

We are not using the FRDM-RW612. We are using a custom Dev Board based on RW612ETA2I. The MCU is the same, but the board layout differs.

The audio codec (PCM6120) is wired to FLEXCOMM3 / I2S3 on the following fixed pins:

Signal GPIO Direction

I2S DATA (SDOUT from PCM6120)	GPIO24	Input
I2S SCK (BCLK to PCM6120)	GPIO25	Output
I2S WS (FSYNC to PCM6120)	GPIO26	Output
I2C SDA (PCM6120 config)	GPIO56 (FC14)	Bidirectional
I2C SCL (PCM6120 config)	GPIO57 (FC14)	Bidirectional
AUX_EN (PCM6120 power)	GPIO54	Output

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3. SDK Version

We are using SDK_2.x_RD-RW612-BGA, version 25.03.00.

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4. Base Example

We used rdrw612bga_i2s_dma_record_playback as the reference example. That example uses FLEXCOMM1 (TX master) + FLEXCOMM0 (RX slave) + I2S bridge, which we confirmed is working.

However, our hardware constraint forces us to use a single FLEXCOMM (FC3 only) for the entire I2S link to PCM6120. PCM6120 must work in Slave mode because we dont have External clock to source for BCLK . We attempted to configure FC3 as kI2S_MasterSlaveNormalMaster to have it generate SCK/WS while receiving data.

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5. UM11865 Section 28.2 – I2S Configuration Steps

We have reviewed UM11865 Section 28.2 and can confirm all 6 configuration
steps are followed:
Step 1: Flexcomm enabled with CLOCK_EnableClock + RESET + CLOCK_AttachClk
Step 2: FIFO configured (FIFOCFG=0x35, ENABLETX=1, SIZE=8)
Step 3: I2S pins set via IO_MUX_SetPinMux(IO_MUX_FC3_I2S), AON MCI_IOMUX enabled
Step 4: Rate configured (CFG1 MSTSLVCFG=0b11=NormalMaster, DIV=3 → BCLK=3.072MHz)
Step 6: DMA enabled in FIFOCFG

Despite following all steps, we observe:
- No SCK/WS edges on GPIO25/GPIO26
- TX FIFO not accepting data: TXNOTFULL=1 but TXLVL stays 0 after FIFOWR writes

Section 28.2 Step 4 states "For controller operation, the clock determines
the I2S rate" but does not specify whether PERSEL=I2S_RECEIVE with
NormalMaster is expected to drive SCK/WS onto the pads.

Can you clarify:
1. Is PERSEL=I2S_RECEIVE (0b101) capable of driving SCK/WS as outputs
when MSTSLVCFG=NormalMaster?
2. Why does TXLVL remain 0 after writes to FIFOWR with PERSEL=I2S_TRANSMIT?
Is MAINENABLE required before FIFOWR writes are accepted?

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6. Observed Issue – Our Specific Question

After all configuration above, GPIO25 and GPIO26 produce zero edges. PCM6120 reports missing clocks (ASI_STS = 0xFF, DEV_STS1 = 0x80).

We further ran a diagnostic: we configured FC3 as I2S TX master (instead of RX master) and found that writes to FIFOWR do not increment TXLVL — FIFOSTAT stays at 0x30 (TXNOTFULL=1, TXLVL=0) regardless of how many words we write.

Relevant register state after TX master probe:

CFG1 = 0x17003C (MSTSLVCFG=3 = NormalMaster, DATALEN=24, MAINENABLE=0)
DIV = 3 (divider=4, BCLK = 12.288MHz / 4 = 3.072MHz)
FIFOCFG = 0x35 (ENABLETX=1, TXI2SE0=1)
FIFOSTAT = 0x30 (TXNOTFULL=1, TXLVL=0 after writes)

After MAINENABLE=1:
STAT = 0x5 (BUSY=1, LR=1 — clock logic running internally)
SCK/WS edges on GPIO25/GPIO26: 0

Our specific question to NXP:

When FLEXCOMM3 I2S is configured as kI2S_MasterSlaveNormalMaster (either TX or RX), is it expected behavior on RW612 that SCK/WS are not driven onto GPIO25/GPIO26 (AON domain), even though STAT shows the peripheral is internally running?

Alternatively: Is a single-FLEXCOMM topology (one FC as both clock master and RX data receiver) supported by the RW612 I2S hardware, or does RW612 always require two separate FlexComm instances (one TX master + one RX slave via I2S bridge) for this use case?

Thank you.

[RomanVR]

Hi @duyhung, thanks for providing additional details of your setup.

Based on the reference manual (RM00278), when the I2S instance is configured in normal master mode, the SCK and WS signals are configured to be generated but not to transmit or receive data, as it is detailed in section 31.1.2 of the RM00278 in CFG1[MSTSLVCFG] register. In the I2S driver, this configuration is applied within the "I2S_TxInit();" function, which also configures the Flexcomm instance being used and the FIFO as a transmitter instance.

Given the previous information, the double Flexcomm topology with shared signals (as it is done in the example you have already tested) is suggested, as it is demonstrated in a similar example shown in Figure 9 in section 3.6.2.1.1 of UM11865.

RomanVR_0-1785886440838.png

Additionally, if you are taking as base the I2S with DMA playback example, would you please share the modifications you have done to the example?