K82 SPI port - unable to set CS as "active low"

[riccardo_maestr]

Hi all,

i have a working SPI bus through two devices. The master is a K82, i'm developing on MCUXPRESSO.

To get it work I have disabled the chip select pin, to keep it low. Fast way is setting the driver to use CS0 that is an unused pin. I'm forced to do that because even if I set CS4 on the driver configuration to work as "active low" it still goes high when the communication starts.

This is part of the code involved:

// Pins muxing (from tool)
CLOCK_EnableClock(kCLOCK_PortA); /* Port A Clock Gate Control: Clock enabled */
CLOCK_EnableClock(kCLOCK_PortC); /* Port C Clock Gate Control: Clock enabled */

PORT_SetPinMux(PORTA, PIN16_IDX, kPORT_MuxAlt2);  /* PORTA16 (pin 46) is configured as SPI0_SOUT */
PORT_SetPinMux(PORTA, PIN17_IDX, kPORT_MuxAlt2);  /* PORTA17 (pin 47) is configured as SPI0_SIN */
PORT_SetPinMux(PORTC, PIN0_IDX, kPORT_MuxAlt2);    /* PORTC0 (pin 70) is configured as SPI0_PCS4 */
PORT_SetPinMux(PORTC, PIN5_IDX, kPORT_MuxAlt2);    /* PORTC5 (pin 77) is configured as SPI0_SCK */

#define WIFI_DSPI_MASTER_BASEADDR SPI0
#define WIFI_MASTER_CLK_SRC DSPI0_CLK_SRC
#define WIFI_MASTER_CLK_FREQ CLOCK_GetFreq(DSPI0_CLK_SRC)
#define WIFI_DSPI_MASTER_PCS_FOR_INIT kDSPI_MasterPcs0 // setting up the wrong one makes the thing work
#define WIFI_DSPI_MASTER_PCS_FOR_TRANSFER kDSPI_MasterPcs0 // same, if i set CS4 it will work inverted
#define WIFI_SPI_TRANSFER_BAUDRATE 500000U
extern dspi_transfer_t spi_WIFI_transfer;
extern dspi_master_config_t spi_WIFI_masterConfig;
extern dspi_master_ctar_config_t spi_WIFI_ctarConfig;

// CTAR config
spi_WIFI_ctarConfig.baudRate = WIFI_SPI_TRANSFER_BAUDRATE; // 500000
spi_WIFI_ctarConfig.bitsPerFrame = 8;
spi_WIFI_ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
spi_WIFI_ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;
spi_WIFI_ctarConfig.direction = kDSPI_MsbFirst;
spi_WIFI_ctarConfig.pcsToSckDelayInNanoSec = 1000000000U / WIFI_SPI_TRANSFER_BAUDRATE;
spi_WIFI_ctarConfig.lastSckToPcsDelayInNanoSec = 1000000000U / WIFI_SPI_TRANSFER_BAUDRATE;
spi_WIFI_ctarConfig.betweenTransferDelayInNanoSec = 1000000000U / WIFI_SPI_TRANSFER_BAUDRATE;

/*Driver configuration and init for SPI*/
spi_WIFI_masterConfig.whichCtar = kDSPI_Ctar0;
spi_WIFI_masterConfig.ctarConfig = spi_WIFI_ctarConfig;
spi_WIFI_masterConfig.whichPcs = WIFI_DSPI_MASTER_PCS_FOR_INIT;
spi_WIFI_masterConfig.enableContinuousSCK = false;
spi_WIFI_masterConfig.enableRxFifoOverWrite = true;
spi_WIFI_masterConfig.enableModifiedTimingFormat = false;
spi_WIFI_masterConfig.samplePoint = kDSPI_SckToSin0Clock;
spi_WIFI_masterConfig.pcsActiveHighOrLow = kDSPI_PcsActiveLow; // THIS IS NOT AFFECTING THE BEHAVIOR OF CS4 PIN!!
DSPI_MasterInit(WIFI_DSPI_MASTER_BASEADDR,&spi_WIFI_masterConfig, WIFI_MASTER_CLK_FREQ);

// comm test (works if I set PCS as PCS0 (unused one), so PCS4 will remain LOW)
spi_WIFI_transfer.txData = masterTxData;
spi_WIFI_transfer.rxData = masterRxData;
spi_WIFI_transfer.dataSize = 4;
spi_WIFI_transfer.configFlags = kDSPI_MasterCtar0 | WIFI_DSPI_MASTER_PCS_FOR_TRANSFER | kDSPI_MasterPcsContinuous;
DSPI_MasterTransferBlocking(WIFI_DSPI_MASTER_BASEADDR, &spi_WIFI_transfer);‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

Attached two screenshots of signal capturing with a logic analyzer.

I will really appreciate suggestions!

Thanks,
Riccardo

[xiangjun_rong]

Hi, Riccardo,

I think you should configure the SPIx_MCR[PCSIS] so that the SPI knows the PCSx logic(low or high) when it transfers data.

In SDK, pls  try to set the line:

typedef enum _dspi_pcs_polarity_config
{
    kDSPI_PcsActiveHigh = 0U, /*!< Pcs Active High (idles low). */
    kDSPI_PcsActiveLow = 1U   /*!< Pcs Active Low (idles high). */
} dspi_pcs_polarity_config_t;

    masterConfig.whichPcs = EXAMPLE_DSPI_MASTER_PCS_FOR_INIT;
    masterConfig.pcsActiveHighOrLow = kDSPI_PcsActiveLow;

This is the code to initialize the PCSIS bits:

void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz)
{
    uint32_t temp;
    /* enable DSPI clock */
    CLOCK_EnableClock(s_dspiClock[DSPI_GetInstance(base)]);

    DSPI_Enable(base, true);
    DSPI_StopTransfer(base);

    DSPI_SetMasterSlaveMode(base, kDSPI_Master);

    temp = base->MCR & (~(SPI_MCR_CONT_SCKE_MASK | SPI_MCR_MTFE_MASK | SPI_MCR_ROOE_MASK | SPI_MCR_SMPL_PT_MASK |
                          SPI_MCR_DIS_TXF_MASK | SPI_MCR_DIS_RXF_MASK));

    base->MCR = temp | SPI_MCR_CONT_SCKE(masterConfig->enableContinuousSCK) |
                SPI_MCR_MTFE(masterConfig->enableModifiedTimingFormat) |
                SPI_MCR_ROOE(masterConfig->enableRxFifoOverWrite) | SPI_MCR_SMPL_PT(masterConfig->samplePoint) |
                SPI_MCR_DIS_TXF(false) | SPI_MCR_DIS_RXF(false);

//////// Rong write: PLS refer to the initialization line

    DSPI_SetOnePcsPolarity(base, masterConfig->whichPcs, masterConfig->pcsActiveHighOrLow);

/////////////////////////////////////////////////////////////////////////

Hope it can help you

BR

Xiangjun Rong

[riccardo_maestr]

Thank you for the suggestion. I went through the code forcing this part of the register configuration (I'm saying "forcing" because it was actually already done from the MasterInit) but the result is the same. I tried to load the standard configuration and only setting PCS4 to be active low, but no luck.

This looks really strange to me.

Riccardo

[xiangjun_rong]

Hi, Riccardo,

do you mean that the PCS4 can toggle normally as the figure you gave, but the logic is incorrect, if the PCS4 is inverted, everything is okay, right?

If it is the case, how about set all PCSIS bits in SPIx_MCR[PCSIS].

BR

Xiangjun Rong