EVK-MIMXRT1050 SDK Cache Coherency Problems

[mikenewton]

Hi,

I have added the HTTP Server demo to the SDK manifest, and successfully compiled and been able to run the demo web server successfully using SDK 2.3.0, with MCUXpresso IDE v10.1.1 [Build 606] [2018-01-02] 

The FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE define was missing, stopping the PHY from initializing, so it fits in RAM. ( I suspect this should be in MIMXRT1052_features.h ).

I think I have modified my project to XIP ( as per "SDK Examples: Converting a RAM project to XIP from Flash" ), and it will execute from a power up without the debugger.

This however only works with SRAM_DTC as the data area. Using SRAM_OC or BOARD_SDRAM results in various problems - typically hanging indefinitely on what appear to be uninitialized semaphores, which seemed to be be cache coherency problems.

I have added the script for the SDRAM init in the debugger, and when editing the MCU memory table used the 'Generate configuration files for debug' to the Debug directory, and also selected 'Refresh MCU Cache' - although just what this achieves and what it sets is unclear to me.

The DTC ram is nearly fully at 128k, so I want to use a larger area - either the 256k OC ram, or for bigger projects the 16MB SDRAM. If I comment out the SCB_EnableDCache(); in BOARD_ConfigMPU(), I can run either in the debugger or standalone from power up in either 256k On chip RAM or 16MB DRAM, but very slow because of the lack of data cache.

I can't find any code other than the BOARD_ConfigMPU() and SystemInit() that accesses any of the Cache or MPU registers

I have tried removing the ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); instead of the SCB_EnableDCache(); but this still failed in the same manner.

I have performed the Mass Erase using the Hello World XIP project, but if I attempt it from this project the dialogue hangs right at the start.

Can anyone provide details of how to manage the Cache configuration for different memory segments / devices for the Data cache?

Thanks

[mikenewton]

Hi,

Thanks for the feedback and referring me to those documents.

The cause of the problem was the Ethernet DMA buffers - the compiler directives don't have any effect under the current MCUXpresso IDE - or at least I couldn't see how to achieve the required memory structure with the IDE. This is probably one of the shortcomings in the early version as to why the Ethernet demo hasn't been released - as well as needing the FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE define do they PHY wouldn't detect and initialize without it.

As a short term, I made the DTCM as RAM2 area, and then used the simple __DATA(RAM2) SDK_ALIGN directive instead for the DMA buffers and structures - I want high Ethernet performance anyway so made sense. Will review with the next IDE / SDK released later in March.

Now getting good Ethernet performance, even with a project combined with the emWin example concurrently.

Thanks

[Yuri]

Hello,

  the Ethernet DMA buffers should be located in non-cached memory. 

According to default linker files it is located as following:

define symbol m_ncache_start = 0x81E00000;
define symbol m_ncache_end = 0x81FFFFFF;

define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];

define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init };

place in NCACHE_region { block NCACHE_VAR };
   

Regards,

Yuri.

[Yuri]

Hello,

   refer to the following app notes:

"Using the i.MXRT L1 Cache"

https://www.nxp.com/docs/en/application-note/AN12042.pdf 

"Using the i.MX RT FlexRAM"

https://www.nxp.com/docs/en/application-note/AN12077.pdf 

Summary Page:

i.MX RT1050 crossover processor| Arm Cortex-M7|NXP 

Have a great day,

Yuri

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