Thanks for your explanation. I don't want to stress this too much but would like to add one final comment:
Our specific problem is not related to interrupt enable/disable state. It's related to the state of the Cortex M4 CONTROL register. Our RTOS configures an alternate stack and then sets bit 1 in this register. If you execute another firmware image while CONTROL is still in this state, the images crashes when the first ISR is executed. But this is only one out of many possible problems than can occur if the CPU is not in a well-defined state when an image is launched.
As I understand your explanation above the overall sequence is:
(1) Application firmware runs and can modify CPU state in any way.
(2) Debug session is started. CPU is in an arbitrary state at this point.
(3) FLASH driver runs. New application image is flashed.
(4) New application image is launched.
To avoid side effects as the one described above, at the transitions (2)->(3) and (3)->(4) there should be a CPU reset.
In our specific case, if there is no reset at (2)->(3) and if the FLASH driver would use interrupts then the FLASH driver would crash. Bad experience too, and much more difficult to debug...
Thanks and regards,
Udo