LPC1347 PWM cycle length issue

[mateuszkiełbasa]

Hi community!

I'd like to write aplication to control PWM with 50Hz frequency and 1ms duty cycle using 16 bit timer. This is my code.

#include "board.h"

#include "../../static/inc/ct.h"
#include <cr_section_macros.h>

#define PRESCALE_VAL 36000 /* f = 72MHz, output T = 0.5ms => output f = 2kHz, 72MHz / 2kHZ = 36000 */

#define TIMER LPC_TIMER16_0
#define SYSCTL LPC_SYSCTL
#define IOCON LPC_IOCON

#define PWM_GPIO_PORT 0 /* PWM output port */
#define PWM_GPIO_PIN 8 /* PWM output pin */
#define IOCON_FUNC_PWM IOCON_FUNC2

#define PWM_MATCH_CHANNEL 0
#define PWM_RESET_CHANNEL 3

   int main(void) {
   // Generic initialization
   SystemCoreClockUpdate();
   Board_Init();

   IOCON->PIO0[PWM_GPIO_PIN] = IOCON_FUNC_PWM;
   SYSCTL->SYSAHBCLKCTRL |= CT16B0_CLOCK_MASK;
   Timer_Reset(TIMER);
   TIMER->PR = PRESCALE_VAL - 1;
   TIMER->MR[PWM_MATCH_CHANNEL] = 38; // 38 * 0.5 = 19ms
   TIMER->MR[PWM_RESET_CHANNEL] = 40; // 40 * 0.5 = 20ms
   TIMER->MCR |= TIMER_RESET_ON_MATCH(PWM_RESET_CHANNEL);
   TIMER->EMR |= _BIT(PWM_MATCH_CHANNEL);
   TIMER->PWMC |= _BIT(PWM_MATCH_CHANNEL) | _BIT(PWM_RESET_CHANNEL);
   TIMER->TCR |= TIMER_ENABLE_MASK;

   while(1) {}
   return 0 ;
}

I'm using logic states analyzer connected to the pwm pin. As a result I see that high state takes exactly 1.5ms (?) and low state takes 19ms (that's ok). My question is why duty cycle takes 1.5ms instead of 1ms?

[jeremyzhou]

Hi Mateusz Kie&#322;basa,

Thank you for your interest in NXP Semiconductor products and 

for the opportunity to serve you.

It seems a bit strange.

I was wondering if you can tell me the cycle time of the match reset, and you can try set 39 instead of 40 likes below code.

TIMER->MR[PWM_RESET_CHANNEL] = 39 ‍

Have a great day,
TIC

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[mateuszkiełbasa]

Thanks for your answer!

I checked and your solution works! Could you tell me why must I subtract one from this register value? It's incomprehensible for me...

Have a great day!