SEMC SRAM ADMUX configuration

[davidfi]

I am using MCUXpresso to select pins for new schematic design.
How do I make MCUXpresso show MIMXRT1064CVJ5B pins for SEMC in SRAM with ADMUX mode pins?

[davidfi]

Hy May.

by "In MCUXpresso Config Tools, you should first route the required SEMC external signals, such as SEMC_ADDRxx and SEMC_DATAxx .
Then configure the SEMC address mode to ADMUX in the SEMC register/peripheral configuration." 

you mean - to use SRAM that has ADMUX like https://www.issi.com/WW/pdf/ADMUX%20SRAM.pdf I should 

use MCUXpresso to connect pins with not "correct" name and pretend I see the correct name in
the "Table 25-6 SEMC Pin Mux Overview  in the RT1064RM" on another column?

If it is not possible to, change the name shone in MCUXpresso SEMC now - just make a request 
Or ask Gemini to fix this in the code for the next version of  MCUXpresso

Thank you!

David.

[mayliu1]

Hi @davidfi ,

No — you don’t need to remap or “pretend” pin names, and this is not an issue with MCUXpresso.

As shown in Table 25‑6, in ADMUX mode the same physical pins (e.g. SEMC_DATAxx) are used as both Dn / An at different phases (e.g. D0/A0). This reflects multiplexing behavior, not a different pin definition.

mayliu1_0-1780650870741.png

In MCUXpresso, SEMC signals are always shown as SEMC_ADDRxx / SEMC_DATAxx. ADMUX is not a pin-mux feature, but an internal SEMC mode configured by registers.

The controller handles the address/data multiplexing internally in ADMUX mode, so the pin naming does not change. This is expected and already aligned with the hardware design model.

BR

May

[davidfi]

I didn't get the difference between SEMC configuration that change pins function of SEMC to other interfaces configuration that changes their pin names.
Is it the same from the user point of view or not?

[mayliu1]

This point can sometimes be confusing, since both cases involve pin configuration.

From a configuration step perspective, you’re right that both cases involve changing pin settings in IOMUX, which can make them look quite similar.

However, from a functional point of view, there is an important difference:

1: SEMC configuration → enables the external memory controller to use those pins;

2:  Other interface configuration → assigns the same pins to a different peripheral (such as GPIO, UART,.....).

So in practice, it’s less about simply “renaming” the pins, and more about selecting which internal peripheral is actually connected to them.

I hope this helps clarify the distinction.

[davidfi]

Wow - Thank you! - The configuration helping tool could be more helpful, if it could do both types of configurations.

[mayliu1]

Hi @davidfi ,

Thank you so much for your interest in our products and for using our community.

ADMUX is not an IOMUX pin function. It is an internal SEMC bus mode for multiplexed address/data.

MCUXpresso Config Tools shows SEMC signals like SEMC_DATAxx and SEMC_ADDRxx , while the ADMUX behavior is determined by SEMC controller configuration (for example  SRAMCR0[AM] ),  not by pin mux selection.

 For more details on the pin configuration, please refer to Table 25-6 SEMC Pin Mux Overview  in the RT1064RM.

mayliu1_0-1780301514849.png

Best Regards

May Liu

[davidfi]

Hi mayliu1

Thank you for your quick replay.

In MCUXpresso pins -> Peripheral Signals -> there is SEMC box.
I would like to see inside SEMC signals in the ADMUX configuration:
instead of ADDR 00 and DATA 00 - a ADDR_DATA_00 pin selection.

davidfi_0-1780302749690.png

How do I change SEMC mode in the MCUXpresso?

[mayliu1]

Hi @davidfi ,

ADMUX is not a pin-mux (IOMUX) option.

It is an internal SEMC address mode. In the rt1064RM reference manual, ADMUX is selected by the SEMC SRAM/NOR control register field (for example, SRAMCR0[AM] , where 00b = Address/Data MUX mode ) rather than by the pin-mux settings.

mayliu1_0-1780644470849.png

In MCUXpresso Config Tools, you should first route the required SEMC external signals, such as SEMC_ADDRxx and SEMC_DATAxx .
Then configure the SEMC address mode to ADMUX in the SEMC register/peripheral configuration.

BR

May