platform clock (ip_clk) on PORESET

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platform clock (ip_clk) on PORESET

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antonsutterluty
Contributor I

On POR what is the platform clock (SYS_PLL_CFG, SYS_PLL_RAT) before RCW is read on a LS1021a?

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ufedor
NXP TechSupport
NXP TechSupport

It is SYSCLK - refer to the QorIQ LS1021A Reference Manual, Figure 4-2. Reset timeline diagram.

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