ls1046a DDR validation

[renaud]

We are doing a design based on the LS1026. The DDR4 will be configured through SPD.

We do not have a Codewarrior ICE so I suppose I cannot run the DDR validation tool.

Is there an application note explaining the algorithm to use to tune up the DDR4?

I suspect the algorithm must loop on CLK_ADUST and WRLVL, run a BIST and see it is passes or not

I do have the QCVS_DDR user guide showing a validation tool.

[ufedor]

You wrote:

> The DDR4 will be configured through SPD.

In this case, if DDR interface PCB layout will be implemented exactly as described in the AN5097 - Hardware and Layout Design Considerations for DDR4 SDRAM, then, normally, no additional optimization will be needed.

> Is there an application note explaining the algorithm to use to tune up the DDR4?

There is no such document.