load_image() function is stuck and cannot continue

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load_image() function is stuck and cannot continue

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muaxi8
Contributor V

my custom board is LX2080。But it executes until the “”load_image“” function and cannot continue.

What is the reason? 

 

bl2_el3_setup 63
NOTICE:  BL2: v2.3():v2.3-LSDK-20.12-dirty
NOTICE:  BL2: Built : 16:21:49, May 26 2021
platform clock 800000000
DDR PLL1 1600000000
DDR PLL2 1600000000
frequency = 800MHz
Vref_phy = 75 percent
Initializing input adv data structure
mr[0] = 0xa34
mr[1] = 0x101
mr[2] = 0x0
mr[3] = 0x0
mr[4] = 0x0
mr[5] = 0x0
mr[6] = 0x0
input->cs_d0 = 0x3
input->cs_d1 = 0x0
input->mirror = 0x0
PHY ODT impedance = 48 ohm
PHY DQ driver impedance = 28 ohm
PHY Addr driver impedance = 30 ohm
odt[0] = 0x1
odt[1] = 0x0
odt[2] = 0x0
odt[3] = 0x0
Initializing message block
msg_blk->dram_type = 0x2
msg_blk->sequence_ctrl = 0x31f
msg_blk->phy_cfg = 0x0
msg_blk->x16present = 0x3
msg_blk->dramfreq = 0x640
msg_blk->pll_bypass_en = 0x0
msg_blk->dfi_freq_ratio = 0x2
msg_blk->phy_odt_impedance = 0x0
msg_blk->phy_drv_impedance = 0x0
msg_blk->bpznres_val = 0x0
msg_blk->enabled_dqs = 0x48
msg_blk->acsm_odt_ctrl0 = 0x1
msg_blk->acsm_odt_ctrl1 = 0x0
msg_blk->acsm_odt_ctrl2 = 0x0
msg_blk->acsm_odt_ctrl3 = 0x0
Initialize PHY 0 config
pll_ctrl2 = 0xb
SOC_SI_REV = 2
dll_lck_param = 0x212
dll_gain_ctl = 0x61
acx4_anib_Dis 0x0
Load 1D firmware
Loading image id=32 at address 0x18003000
Image id=32 loaded: 0x18003000 - 0x18009bd0
.Loaded Imaged id 32 of size 6bd0 at address 18003000
Loading image id=34 at address 0x18003000
Image id=34 loaded: 0x18003000 - 0x180036d0
.Loaded Imaged id 34 of size 6d0 at address 18003000
Execute firmware
Applying PLL optimal settings
pll_ctrl2 = 0xb
pll_ctrl1 = 0x21
pll_test_mode = 0x24
pll_ctrl4 = 0x17f
End of fine write leveling
1D Training completed
CDD rrmax 3 wwmax 4 rwmax 2 wrmax 0
ret : 0  input.basic.train2d= 0 Load PIE
seq0bdly0 = 0x32
seq0bdly1 = 0x64
seq0bdly2 = 0x3e8
seq0bdly3 = 0x2c
NOTICE:  DDR4 UDIMM with 1-rank 64-bit bus (x16)
dram_size = 4294967296Program controller registers
twopass=0
PHY handshake completed, timer remains 39
total size 4 GB
Need to wait up to 1320 ms
*0x1080000 = 0xff
*0x1080080 = 0x80010412
*0x1080100 = 0x12591100
*0x1080104 = 0x8c880013
*0x1080108 = 0xe0ed474
*0x108010c = 0x6151e6
*0x1080110 = 0xe5240000
*0x1080114 = 0x401020
*0x1080118 = 0x1010a34
*0x1080124 = 0x24900924
*0x1080160 = 0x102
*0x1080164 = 0x11401400
*0x108016c = 0x27750000
*0x1080170 = 0x8a090705
*0x1080200 = 0x180000
*0x1080224 = 0x702
*0x1080228 = 0x8000000
*0x1080250 = 0x5228a00
*0x1080800 = 0x43b30002
*0x1080804 = 0x1f1f1f1f
*0x1080b24 = 0x4
*0x1080bf8 = 0x20505
*0x1080f04 = 0x102
*0x1080f0c = 0x124a02c0
*0x1080f48 = 0x1
*0x1080f4c = 0x94000000

NOTICE:  4 GB DDR4, 64-bit, CL=16, ECC on
get_dram_regions_info over
mmap_add_ddr_region_dynamically end
DDR Controller 1.
DDR Controller 2.
bl2_load_images begin
BL2: Loading image id 3
Loading image id=3 at address 0xfbe00000

 

 

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yipingwang
NXP TechSupport
NXP TechSupport

Please refer to the following TF-A BL2 boot flow

a. BL2 initializes the DRAM, configures TZASC
b. BL2 loads  BL31, BL32, and BL33 images to the DDR memory after validating these images BL31, BL32, and BL33 images form FIP image, fip.bin.
c. Post validation of all the components of the FIP image, BL2 passes execution control to the EL3 runtime firmware image named as “BL31".

Because there is problem at DDR controller initialization, so it is impossible to load BL31, BL32, and BL33 images to the DDR memory.

View solution in original post

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yipingwang
NXP TechSupport
NXP TechSupport

Please refer to the following TF-A BL2 boot flow

a. BL2 initializes the DRAM, configures TZASC
b. BL2 loads  BL31, BL32, and BL33 images to the DDR memory after validating these images BL31, BL32, and BL33 images form FIP image, fip.bin.
c. Post validation of all the components of the FIP image, BL2 passes execution control to the EL3 runtime firmware image named as “BL31".

Because there is problem at DDR controller initialization, so it is impossible to load BL31, BL32, and BL33 images to the DDR memory.

View solution in original post

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muaxi8
Contributor V

Could you please send me a fip_ddr.bin file, I suspect there is something wrong with my fip_ddr.bin

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yipingwang
NXP TechSupport
NXP TechSupport
 
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muaxi8
Contributor V

My custom board now uses the first DDR controller. Does the software need to be modified?

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yipingwang
NXP TechSupport
NXP TechSupport

If you use different type DDR from the demo board, you need to modify DDR controller configuration.

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