how to use qspi_b in LS1046a

[yenchao]

Hi,

I have a ls1046a carrier board and would like to use QSPI_B (used as SPI, i.e., only QSPI_B_SCK, QSPI_B_DATA0 and QSPI_B_DATA1 are used) to connect mcp2518fd(spi to can controller).

It seems like &qspi in fsl-ls1046a-rdb.dts is QSPI_A, so how to configure QSPI_B?

Thx

Yen

[yenchao]

Hi NXP,

Any advices?

Thx

Yen

[Chavira]

Yes. It is possible to connect two QSPI in the LS1046A.
Actually, LS1046A can work with up to 4 flashes as you already pointed to the CS.
The qSPI boot, however, has to boot from qSPI A, which uses SPI_A_CS0. Whether you want to connect the 2nd flash to which one, really depends on customer design. You can connect to any of the 3 CSs. The DTS file has to match the hardware design.

[yenchao]

Hi,

I would like to know where to add mcp2518fd node in fsl-ls1046a-rdb.dts.

Is this correct?

&qspi {
	status = "okay";
// added by Yen for mcp2518fd	
        can@2 {
            compatible = "microchip,mcp2518fd";
            reg = <2>;
            clocks = <&mcp2518fd_osc>;
//            pinctrl-names = "default";
//            pinctrl-0 = <&can0_pins>;
            spi-max-frequency = <20000000>;
//            interrupts-extended = <&gpio 13 IRQ_TYPE_LEVEL_LOW>;
            microchip,rx-int-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
            vdd-supply = <&sb_3v3>;
//            xceiver-supply = <&reg5v0>;
        };	
////
};

If yes, how can I assign it to QSPI_B?

If I am wrong, please advice where to add mcp2518fd node and assign it to QSPI_B.

Thx

Yen

[yenchao]

Hi

Any updates for how to add mcp2518fd node into device tree?

Thx

Yen

[Chavira]

Please refer to arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts and arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts and fsl-ls1046a.dtsi. In the later file, it already defined following:

qspi: spi@1550000 {
compatible = "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x1550000 0x0 0x10000>,
<0x0 0x40000000 0x0 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "qspi_en", "qspi";
clocks = <&clockgen 4 1>, <&clockgen 4 1>;
status = "disabled";
};
In the first file, a specific flash device can be defined as following example.
s25fs512s1: flash@1 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <1>;
spi-tx-bus-width = <1>;
reg = <1>;
};

On LS1046A, qSPI interface only support 1.8V.
By the way, I could be wrong, I do not recommend to use qSPI to connect mcp2518fd. The SPI interface would be proper for this device.

[yenchao]

Hi

We have a voltage level translator, so the voltage is not a problem.

Please advise how to assign mcp2158fd node to QSPI_B.

(It seems like default is QSPI_A)

Thx

Yen

[Chavira]

You can manage two QSPI from node A because we have two chip selects in node A.

We can be sure if that memory can work due to the level Voltage, I know that issue was resolved with level shifters but originally the memory is not supported for the MPU.

[yenchao]

Hi,

We would like to add mcp2518fd to QSPI node B, not node A.

Please help us how to assign mcp2518fd to QSPI node "B" in dts file

Thx

Yen

[Chavira]

It can be either A or B. The register settings in qSPI_SFxyAD determined the memory location. Therefore, qSPI controller will access proper flashes if SW gives a valid location according to where this location address resides in which flash memory range.

[yenchao]

Hi

Is this correct for assigning mcp158fd to QSPI_B in fsl-ls1046a-rdb.dts?

&qspi {
	status = "okay";

	s25fs512s0: flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
		spi-rx-bus-width = <1>;
		spi-tx-bus-width = <1>;
		reg = <0>;
	};

	s25fs512s1: flash@1 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
		spi-rx-bus-width = <1>;
		spi-tx-bus-width = <1>;
		reg = <1>;
	};
	
// added by Yen for mcp2518fd	
        can@2 {
		compatible = "microchip,mcp2518fd";
		reg = <2>;
		clocks = <&mcp2518fd_osc>;
		spi-max-frequency = <20000000>;
                microchip,rx-int-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
		vdd-supply = <&sb_3v3>;
		xceiver-supply = <&sb_5v0>;			
        };	
////	
};

[yenchao]

Hi

Any updates?

Thx

Yen

[yenchao · Accepted solution]

Hi

The answer is 

- reg: There are two buses (A and B) with two chip selects each.
This encodes to which bus and CS the flash is connected:
<0>: Bus A, CS 0
<1>: Bus A, CS 1
<2>: Bus B, CS 0
<3>: Bus B, CS 1

Thx

Yen