e200z7260n3 reference manual

[NigelP]

Hi,

I'm looking for documentation on the e200z7260n3 processor as contained within the LA1224 device.

In particular I'm currently trying to understand the MPU setup but have been unable to find documentation for it. I've found documentation for the e200z759n3 but the MMU section in that document does not match the MPU code I have. The application note AN12177.pdf does seem to match the code I have but it would be good to have exact bit definitions.

Thanks

Nigel

[Hector_Villarruel]

Hello @NigelP 

Hope this email finds you well,

Please find attached on the the "e200z760n3 Power Architecture® Core Reference Manual".

I highly recommend you to check the section"10.7 MMU Control Registers" ,"10.10 Effect of Hardware Debug on MMU Operation" from the RM.

I would also like to provide you at the following link just as a reference the application note AN4341 "Using the Performance Monitor Unit on the e200z760n3 Power Architecture Core"

https://www.nxp.com/docs/en/application-note/AN4341.pdf

Have a great day.

BR,

Hector V

[NigelP]

Hi Hector,

Thanks for the reply but the documentation for the e200z760n3 also does not match what I am seeing for the e200z7260n3 based code.

For example looking at the format of MAS0 register is very different, the AN12177 note (https://www.nxp.com/docs/en/application-note/AN12177.pdf) in section 7.1.2 lists 12 fields for this register that does seem to match the code. The field definitions for MAS0 in the e200z760n3 (section 10.7.3) has only 3 fields, none that seem to match the application note.

Thanks

Nigel

[Hector_Villarruel]

Hello @NigelP 

Hope this post finds you well,

Please note that this is an implementation of the S32R274,

As you can see on the AN12177 the application note indicates the following:

This application note will focus on the S32R274 MCU

Regarding such implementation, that is the main reason why the registers are not lined with the core reference manual.

Have a great day.

[NigelP]

Hi,

So does that mean there is no reference manual for the Zen z7260n3?

The reference code I have is from NXP and it runs, so I'm guessing it is doing the right thing but it is not writing the MPU registers anything like what is documented in the e200z760n3 reference manual. For example in the code bit 1 of MAS0 is the guarded bit, according to e200z760n3 reference manual the guarded bit is in MAS2, bit 30. In the code MAS2 is the end address and MAS3 is the start address.

Is that because I want information on the Core MPU rather than the System MPU?

Thanks

[Hector_Villarruel]

Hello @NigelP 

Hope this email finds you well,

I would like to make an mention that the application note AN12177 is focused on the S32R274

Regarding your questions from the last reply:

Any MPU programming syntax used in this application note has been simplified to show the value to be programmed in one line, but for correct compilation would require the 32-bit value to be written first to a general purpose register

Please note the following information from the Application note.

The Core MPU is separate to the System MPU (SMPU) which also exists on the device, and provides extra protection coverage to ensure that all activity within the device is protected. Full SMPU configuration is not included in the scope of this application note

So does that mean there is no reference manual for the Zen z7260n3?

No, there is not.

I recommend you to check the section 16.1 Overview of the e200z7260n3 core from the S32R274/S32R264 Series Reference Manual, Rev. 5, 09/2019

Is that because I want information on the Core MPU rather than the System MPU?

Yes It is.

If there is any further question regarding S32R I highly recommend you to create a new technical support case.

Have a great day.

BR,

Hector Villarruel