Unable to boot LX2160A processor out of PBI and DDR reset is low always

[Nikhiln]

Hi,

We are using LX2160A in our custom board. Processor is not booting (DDR reset is low)
Our configuration is:
DDR4 x32bit @2600MTPS on both controllers.
Flex SPI is the RCW SRC.

HRESET is going high and ASLEEP is low.
When we try to read the registers as per LX2160ARM we are getting below value
0x01E001FC (DCFG_SCRATCHRW3): looks like no error code
+0 +4 +8 +C
[0x01E001E4] 00000000 00000000 00000000 00000000
[0x01E001F4] 00000000 00000000 00000000 00000000
[0x01E00204] 00000000 00000000 00000000 00000000
[0x01E00214] 00000000 00000000 00000000 00000000
[0x01E00224] 00000000 00000000 00000000 00000000

0x01E6_0104 (RCW_COMPLETIONR): Service Processor has completed the RCW loading
0x01E6_0114 (PBI_COMPLETION): Service Processor has complete the PBI phase, also Service Processor Core is in Boot Holdoff and not released for Booting
+0 +4 +8 +C
[0x01E600F0] 00000000 00000000 00000000 00000000
[0x01E60100] 00000000 00000001 00000000 00000000
[0x01E60110] 00000000 00000001 00000000 00000000
[0x01E60120] 00000000 00000000 00000000 00000000

We are unable to boot DDR or validate DDR using DDRv tool in QCVS or get any UART prints

What may be the possible cause of this issue?

Do we need to modify any other registers other than RCW for processor to boot?

[yipingwang]

Please ask them to share
1. Reset register dump (0x1e6_0000 to 0x1e6_0bfc)
2. RCW and PBI file.
3. Schematic
Please ask customer the following:
1. Using CCS, please ask them to configure config chain
delete all
config cc cwtap //for USB (if IP address is present config cc cwtap:<ip_addr>)
show cc
ccs::config_chain {lx2160a dap}
display ccs::get_config_chain
Based on this we can understand if processor is out of reset or not.
2. Are they not able to get any UART prints?
Even before DDR prints some info related to BL2 is printed.
3. Please check whether ddr_phy_firmware is present in the firmware image that they are programming.
Check 0x800000 offset of Flash.

On first instance, I would like to check UART and then DDR.
Because if DDR initialization has failed then some prints related to DDR initialization would have come.

[Nikhiln]

Please ask them to share

1. Reset register dump (0x1e6_0000 to 0x1e6_0bfc)

>>> File attached. File name: register_dump_1e6_log.txt

2. RCW and PBI file.

>>> File attached. File name: PBL_binary.bin

I'm not adding any PBI commands as I'm using NOR flash to boot.

3. Schematic

>>> File attached. File name: LX2160A_SCH

Please ask customer the following:

1. Using CCS, please ask them to configure config chain

delete all

config cc cwtap //for USB (if IP address is present config cc cwtap:<ip_addr>)

show cc

ccs::config_chain {lx2160a dap}

display ccs::get_config_chain

Based on this we can understand if processor is out of reset or not.

>>> File attached. File name: ccs_command_log

2. Are they not able to get any UART prints?

Even before DDR prints some info related to BL2 is printed.

>>> No. Unable to get any prints from UART 1. Probed UART 0 signals, there was no activity observed on scope also.

3. Please check whether ddr_phy_firmware is present in the firmware image that they are programming.

Check 0x800000 offset of Flash.

>>> I'm not flashing any firmware. I'm not able to get the ddr_phy_firmware file. From where I will get the file required.

Clarification:

1. I'm using discrete DDR IC soldered on board, not DIMM modules.

2. I'm using NOR flash as RCW source and for boot.

I have some doubts:

1. I have tried changing RCW configuration, also tried running DDRv tool in QCVS. There was no improvement.

2. In beginning I have mentioned there was an error code as per register 0x01E60114 (PBI_COMPLETION), what does that mean? does it mean PBI image is not proper or image missing?

3. What may be the cause for no activity in UART signals.

4. How will I get the ATF BL2 and BL31 images from?

5. Which all configurations i need to make in order to get the processor to initialize DDR properly.

6. Is it possible to get image with minimal interfaces, just for checking DDR only so that I can use it to flash on the board and check or use it as my reference.

[yipingwang]

In your original description, it seems that using your original RCW, the processor is out of reset successfully.

Would you please use your original RCW values in LSDK 21.08 build environment?

[Nikhiln]

I tried the original RCW in LSDK 21.08 build environment as suggested by you. The result is still the same. HRESET is going high but ASLEEP is staying high.

Original RCW was developed in QCVS tool, it generates PBL_binary.bin, when I flash that image then HRESET is going high and ASLEEP is going low. Same parameters I'm defining in LSDK environment, and it is not working.

I also tried 2 more other rcw settings that work with bin file generated using QCVS but not using LSDK 21.08 environment.

I have mentioned some error while building rcw image using "flex-builder rcw -m lx2160ardb_rev2", it is asking for GitHub credentials, and it is failing when I enter username and password. Will that cause any issues?

What are the things processor checks before it drives ASLEEP zero?

[yipingwang · Accepted solution]

Please rebuild RCW with command

$ flex-builder -c rcw -m lx2160ardb_rev2

2. $ flex-builder -c rcw -m lx2160ardb_rev2

Please modify RCW file components/firmware/rcw/lx2160ardb_rev2/XGGFF_PP_HHHH_RR_19_5_2/rcw_2200_750_3200_19_5_2.rcw according to your target board.

$ flex-builder -c rcw -m lx2160ardb_rev2

I am analyzing the RCW and PBL.
Meanwhile, I would like to confirm the following:
1. UART logs says transmission is successful. You are able to see the print on console? or any toggling on oscilloscope?
You are able to do this when booting from nor?
2. Can you try booting the board with disabling serdes and removing PBI commands?

[Nikhiln]

2. Can you try booting the board with disabling serdes and removing PBI commands?

>>> I tried disabling serdes and removing PBI commands as suggested, I'm able to get UART prints, HRESET is high and ASLEEP is also low. UART log is attached below. But DDR initialization is failing. I checked MRST pin from processor it is low. It is not going high anytime. Do I need to add any other configuration for DDR initialization?

What are the configurations required for DDR initialization?

I'm using both controllers, 4GB DDR4 with 32bit width without ECC on each controller. All connections are one-to-one, no bit or byte swapping in DDR controllers. I have shared the schematic during initial conversation in this post itself.

Attaching the RCW used to get the UART prints.

Also, I tried the pbl file shared by you in previous post, HRESET is low when I try to boot.

[yipingwang]

Would you please create a new thread to continue to discuss DDR bringing up issue? This thread was updated too long. DDR bringing up is  another topic and complex.

[Nikhiln]

With new build commands, result is still looks same. I'm trying multiple rcw combinations with the new commands. I will share the results of the same.

1. UART logs says transmission is successful. You are able to see the print on console? or any toggling on oscilloscope?
You are able to do this when booting from nor?

>>> I couldn't get which UART logs you are saying, I'm assuming CCS logs I shared last week using UART commands. I was able to get it working by flashing "PBL_binary.bin" file generated using QCVS tool using the originally shared rcw configuration. I'm not getting any UART prints or observe any toggling in oscilloscope at that time. I was able to observe toggling after manually modifying registers 0x21c0024, 0x21c0028, 0x21c002c registers to 0x5e, 0x3c, 0x70 respectively in ccs.

2. Can you try booting the board with disabling Serdes and removing PBI commands?

>>> I'm using the attached rcw file for disabling Serdes and removing PBI commands. I hope I'm doing it right.

[yipingwang]

I generated ATF image bl2_flexspi_nor.pbl with your original PBL image, please try whether you can get output information from UART1(NOR UART0).

[Nikhiln]

Can you confirm if RCW I shared for serdes disabled and PBI commands removed is valid?

[yipingwang]

Investigating.

[Nikhiln]

But it is used as a debugging experiment. it uses 600MTps of ddr frequency and all other clocks are as low as possible. I will try using the same rcw in lsdk.

Should I have to define PBI length value in rcw? or it will be defined by lsdk while building? I see some PBI commands added while building the rcw files.

Also, where I have to configure DDR configurations like timing parameters for DDR controller?

[yipingwang]

No need to define PBI length value, it will be generated automatically while building.

DDR controller configuration is configured in ATF source code, you need to decide these parameters with QCVS DDRv tool.

First, please check whether there is console output from ATF BL2 running in OCRAM.

Then consider DDR configuration issues.

[Nikhiln]

Okay, I will try the same RCW in lsdk.

We are not using USB in our design and USB related powers are not given. These pins are tied to ground. This is being done as per the recommendation in "AN5407_Design checklist" document.

Also, I recently found "AN12114 - Implementation of IEEE 1149.6 on LX2160A_Rev.C" document which needs to be implemented.

I'm not able to understand this document properly. Can you confirm do I have to add any additional setting or configuration related to USB while building the images?

What does "AN12114 document" is about exactly?

[yipingwang]

No need additional settings for USB while building the image.

[yipingwang]

RCW seems fine, pin mux setting for UART is correct.
SoC is out of reset. Chain on CCS is fine too.

0x01E60114 (PBI_COMPLETION) -- there was no error code reported
For further debugging the issue, we will first check whether UART is working or not and then will move to DDR.

For checking UART, please run the following commands on CCS
display ::ccs::read_mem 86 0x21c0000 4 0 0x10 //UART1 registers
display ::ccs::write_mem 86 0x21c0000 4 0 0x65
display ::ccs::write_mem 86 0x21c0000 4 0 0x66

Before transmitting please set UARTCR[UARTEN] (0x21c0030)

Hope this help.

[Nikhiln]

I tried running these commands but I got all zeros when I read the registers. looks like it is unable to read.

Also, when I try to configure a chain using ccs::config_chain {lx2160a dap} command then I'm getting error: Core not responding.

There is some other issue also. when we keep the RCW_SRC in NOR flash mode processor is releasing HRESET. but when we change it to Hard coded mode then HRESET is always low. Unable to get why this is happening. this issue started a week ago when we flashed an image which had some wrong configuration of RCW in it. What may be causing this issue?

[yipingwang]

For using LSDK, please make sure that you have modify RCW file with the following step correctly. Please configuring the target board as booting from flexspi NOR flash, please don't configure it as hard-coded RCW.

2. $ flex-builder -c rcw -m lx2160ardb_rev2

Please modify RCW file components/firmware/rcw/lx2160ardb_rev2/XGGFF_PP_HHHH_RR_19_5_2/rcw_2200_750_3200_19_5_2.rcw according to your target board.

$ flex-builder rcw -m lx2160ardb_rev2

[Nikhiln]

Hi @yipingwang

I have tried generating the pbl and uboot file as per the procedure suggested by you and flashing in location 0x00000000 and 0x00100000 both files. now processor is releasing HRESET (going High) but ASLEEP is staying high. So, for safer side I disabled the serdes completely in rcw file and the result is same. attached both rcw and flash images generated as per your recommendation (lsdk provided by you and Ubuntu 20.04.6 in VM). Is there anything I'm missing in rcw configuration?

There was an error as explained earlier while building rcw file. It was asking for username and password for some github repositories, log of the same is also attached.

Also, I tried UART commands given by you. Directly it was not working even after I set the UARTEN (0x21c0030). I had to modify 0x21c0024, 0x21c0028, 0x21c002c registers to 0x5e, 0x3c, 0x70 respectively. above 3 registers were 0x00000000 before modification. Log of the same is also attached. This is same with both UART0 and UART1.

Please guide how to proceed further and what may be the issue?

[yipingwang]

Discussing with the AE team.