Strange results in QCVS generated code for DDR init

[altu]

Good day!

I'm performing the build of ATF bootloader from scratch, including DDR calibration on LS1046 ARDB board. The RCW is taken from NXP github - rcw_1800_sdboot.rcw, QCVS tool - version 4.27.00

The calibration on this RCW is successfully passed, and I receive code for DDR init. The values are quite similar to the reference ls1046ardb code from ATF git repo, execept NXP_DDRCLK_FREQ:

In NXP ATF git repo - ##define NXP_DDRCLK_FREQ 10000000

In code from QCVS - ##define NXP_DDRCLK_FREQ 105000000

With reference NXP_DDRCLK_FREQ the board successfully boots.

With QCVS-generated NXP_DDRCLK_FREQ the boot is failed. It seems to me that QCVS is confusing the meaning of  NXP_DDRCLK_FREQ.

In CVS world - NXP_DDRCLK_FREQ - DDR bus clock(base memory clock after multipliers).

In real world - NXP_DDRCLK_FREQ - base Memory clock.

Please explain the situation.

[Bio_TICFSL]

Hello,

The failure when using the QCVS-generated

NXP_DDRCLK_FREQ ( ) on the LS1046ARDB, while works, is likely due to a mismatch between the QCVS-calculated data rate/timing parameters and the actual board's reference clock ( ) defined in the RCW. The QCVS tool, for DDR4, often generates NXP_DDRCLK_FREQ as the base memory clock ( ), which must match the RCW and PLL settings.

Analysis of the Situation:

• RCW rcw_1800_sdboot.rcw: This file dictates the system clock settings, typically setting the DDR reference clock to .
• Reference ATF Value ( Corresponds to a standard input clock, allowing standard or DDR timing calculations to match the hardware PLL.
• QCVS Value ( If QCVS calculated a slightly higher clock ( ), it assumes the PLLs are configured to generate that frequency. If the RCW still provides , the DDR controller is improperly clocked, causing training failures (e.g., or timeout).
• Resolution: Change the NXP_DDRCLK_FREQ in ddr_init.c back to ( ) to match the reference RCW. Ensure all other timing values generated by QCVS are updated based on this correct input clock. 

Actionable Steps:

1. Verify the sys_pll settings in the rcw_1800_sdboot.rcw file to confirm the DDR clock source is .
2. Update the ATF plat/nxp/soc-ls1046a/ls1046ardb/ddr_init.c to use 100000000 for NXP_DDRCLK_FREQ.
3. Ensure the generated ddr_init structure in ddr_init.c is fully updated with the rest of the QCVS output (timings, controllers) while keeping the frequency at . 

Regards

[altu]

So does it mean that QCVS generates the wrong code?

Here we can see a memory clock - the base clock for DDR memory system.

Here we can see a DDR bus clock / DDR data rate , which is produces by DDRCLK x multiplier (21). This multiplier is set by RCW - the parameter is called MEM_PLL_RAT.

1050.000.000 Hz (1050 MHz) - is DDR bus clock (DDR data rate / 2 - 2100 / 2).

In all ATF sources,which are definetely OK(succsessful boot) - NXP_DDRCLK_FREQ = 100000000 (100 Mhz), which clearly correspond with the first picture - on which we can see Memory clock(DDRCLK) = 100000000(100 Mhz).

But QCVS gives a completely different value - NXP_DDRCLK_FREQ = 1050000000(1050 MHz). This value seems to be wrong, because ATF simply fails to boot with it. So please confirm - are my conclusions correct or not?

[Bio_TICFSL · Accepted solution]

Hi,

Based on your description and the behavior of the ATF (Arm Trusted Firmware) failing to boot,

your conclusions are correct. The QCVS tool has likely generated an incorrect value for NXP_DDRCLK_FREQ.

Here is the breakdown of the situation based on standard NXP Layerscape/QorIQ DDR configuration practices:

Analysis of the Conflict

• Memory Clock (DDRCLK): As shown in your clk1.png, the physical oscillator providing the base clock to the DDR controller is 100 MHz (100,000,000 Hz).
• DDR Data Rate / Bus Clock: As shown in clk2.png, the DDR bus clock (or data rate halved) is 1050 MHz (1050.000.000 Hz).
• ATF Behavior: The successful boot configuration uses NXP_DDRCLK_FREQ = 100000000 (100 MHz).
• QCVS Behavior: QCVS is setting NXP_DDRCLK_FREQ = 1050000000 (1050 MHz). 

Why QCVS is Wrong

The NXP_DDRCLK_FREQ parameter in the RCW (Reset Configuration Word) or DDR initialization code refers to the input frequency of the oscillator (the 100 MHz clock), not the resulting memory bus speed (1050 MHz). 

By setting NXP_DDRCLK_FREQ to 1050 MHz, the DDR controller assumes the input clock is much faster than it actually is. Consequently, it calculates wrong internal PLL multipliers and timing registers, leading to a failed memory initialization (DDR training failure), which causes the ATF to halt. 

Recommendations

1. Correct the QCVS Parameter: In the QCVS DDR configuration wizard, under the "DDR Properties" or "Clock" section, ensure that the input clock frequency is explicitly set to 100 MHz (100,000,000 Hz), even if the target data rate is 2100 MT/s (1050 MHz).
2. Verify MEM_PLL_RAT: Ensure that the MEM_PLL_RAT in the RCW is set to a value that multiplies your 100 MHz input to reach your target bus clock (e.g., if input is 100MHz, MEM_PLL_RAT should be around 21 to get 2100 MT/s or 1050MHz bus clock).
3. Use "Import from Target": If you have a working setup, you can import the existing DDR registers from U-Boot into QCVS to ensure the correct values are used in future generated code

regards

[altu]

Thank you for the answer. The situation is clear to me now.Hope the issue will be fixed in future releases of QCVS.

Best regards,