Sample code wanted for configuring p1010 L2SRAM as pure SRAM and executing program code from it?

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Sample code wanted for configuring p1010 L2SRAM as pure SRAM and executing program code from it?

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samedwards
Contributor II

Is there any sample code for configuring p1010 L2SRAM as pure SRAM and executing program code from it?

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samedwards
Contributor II

Not answered yet.

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sinanakman
Senior Contributor III

Hi Sam

How are you intending to run the code for setting l2sram ?

I use a BDI3000 JTAG debugger and with it I can initialize

this as follows :

; Move the 256kB L2SRAM to the initial MMU page

WM32 0xFF720E44 0x0000001C ;L2ERRDIS: disable parity error

WM32 0xFF720000 0x50010000 ;L2CTL

WM32 0xFF720100 0xFFFC0000 ;L2SRBAR0: map to 0x0_FFFC0000

WM32 0xFF720104 0x00000000 ;L2SRBAREA0

WM32 0xFF720000 0x90010000 ;L2CTL

;

; load and execute some boot code

WM32 0xfffffffc 0x48000000 ;loop

EXEC 0xfffffffc

Perhaps this gives you an idea and you can transform it

to your usage.

Regards

Sinan Akman

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samedwards
Contributor II

Hi Sinan,

Thank you for your reply. I intend to run the code in the spl.s program, in the section prior to where spl copies itself from NAND to RAM and continues execution. Presently it is written to copy itself to SDRAM, I want it to execute from SRAM instead. I will translate your sample to the equivalent syntax and report back the results.

Kind regards,

Sam

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sinanakman
Senior Contributor III

Hi Sam

I am not sure which spl.s you are referring to but if

you like you can find the spl code that does this

in mainline u-boot/arch/powerpc/cpu/mpc85xx/spl_minimal.c

Look at the section enabled with CONFIG_SYS_INIT_L2_ADDR.

Hope this helps

Regards

Sinan Akman

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samedwards
Contributor II

Hi Sinan,

Thank you for providing the spl_minimal.c code reference. My application uses VxWorks’ RTOS and the spl is part of the custom bsp provided by WindRiver.

Best,

Sam

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sinanakman
Senior Contributor III

Hi Sam

OK so this is from VxWorks. The code should

work there as well, you just need to make sure

it lined up well with the address space it is setting

and that there is no clash for L2SRAM.

Regards

Sinan Akman

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