Problem with DDRv tool on LS1088A

[joshuam]

Hi, I am trying to validate a new type of DDR4 SO-DIMM on a custom board based on LS1088A SoC, but I am encountering problems with DDRv. I have already validated several other models of DDR4 in the past, and I did not encounter any problems.

The new model of DDR that I am trying to validate is IMM2G72D4SOD8AG-B075I from Memphis. Its speed-grade is 2,666, but we would like to run it at 2,100 MT/s. I have created a new QorQ configuration project and successfully read DDR configuration via SPD. However, the first step (Centering the clock) consistently fails at 0.04%, on the 'Auto search & detect for write leveling start values' part.

In the Test Results summary, I see that the test failed with the reason: "DDR interface is failing due to an issue other than WRLVL_START values, please investigate HW issues on the board."

In the Logs section, I see the following information:

#################### Result for: wrlvl_searcher ###### Run  1 ######################################

Test result: [

============================================================

Updated: WRLVL_CNTL = 0x86550605, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000

============================================================

Updated: WRLVL_CNTL = 0x86550607, WRLVL_CNTL_2 = 0x09060C0F, WRLVL_CNTL_3 = 0x0E110B0E, SDRAM_CLK_CNTL = 0x02800000

============================================================

Updated: WRLVL_CNTL = 0x86550607, WRLVL_CNTL_2 = 0x09050C0F, WRLVL_CNTL_3 = 0x1611130E, SDRAM_CLK_CNTL = 0x02800000

DDR interface is failing due to an issue other than WRLVL_START values, please investigate HW issues on the board.

<<Test failed!>>

{{DDR interface is failing due to an issue other than WRLVL_START values, please investigate HW issues on the board.}}

Err. capture registers:

0xE20, 0x00000000     0xE24, 0x00000000     0xE28, 0x00000000     0xE40, 0x00000080     

0xE44, 0x00000000     0xE48, 0x0000001D     0xE4C, 0x00000000     0xE50, 0x00000000     

0xE54, 0x00000000     0xE58, 0x00010000     

Dump:

0xF00, 0x00000000     0xF04, 0x00001002     0xF08, 0x0000000A     0xF0C, 0x14000C20     

0xF10, 0x00000000     0xF14, 0x00000000     0xF18, 0x00000000     0xF1C, 0x00000000     

0xF20, 0x00000000     0xF24, 0x2F003500     0xF28, 0x2A003600     0xF2C, 0x3E004A00     

0xF30, 0x44004600     0xF34, 0x3A007000     0xF38, 0x00000000     0xF3C, 0x00000000     

0xF40, 0x00000000     0xF44, 0x00000000     0xF48, 0x00000001     0xF4C, 0x94000000     

0xF50, 0x0F001300     0xF54, 0x0C001800     0xF58, 0x1F002C00     0xF5C, 0x22002700     

0xF60, 0x1C000000     0xF64, 0x00009000     0xF68, 0x00000020     0xF6C, 0x00000000     

0xF70, 0x0060007B     0xF74, 0x00000000     0xF78, 0x00000000     0xF7C, 0x00000000     

0xF80, 0x00000000     0xF84, 0x00000000     0xF88, 0x00000000     0xF8C, 0x00000000     

0xF90, 0x00000000     0xF94, 0x80000000     0xF98, 0x00000000     0xF9C, 0x29002B00     

0xFA0, 0x2B002B00     0xFA4, 0x27002D00     0xFA8, 0x28002E00     0xFAC, 0x27000000     

0xFB0, 0x10000003     0xFB4, 0x42344241     0xFB8, 0x40334332     0xFBC, 0x43404150     

0xFC0, 0x00004133     0xFC4, 0x44424444     0xFC8, 0x44415134     0xFCC, 0x51414251     

0xFD0, 0x42414241     0xFD4, 0x50434252     0xFD8, 0x50444342     0xFDC, 0x42413444     

0xFE0, 0x43514340     0xFE4, 0x44424444     0xFE8, 0x42514441     0xFEC, 0x40423443     

0xFF0, 0x43424342     0xFF4, 0x43415042     0xFF8, 0x51415341     0xFFC, 0x54000D0D     

Data: 

0x00000005 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 

]

I have attached the verbose CCS log from the failed validation procedure as well.

Could you please explain what this means and how we can debug the issue?

[db16122]

Compare with new type of DDR4 SO-DIMM, what kind of SODIMM used before? Any change between the new one and the old one

[Bio_TICFSL]

Hello,

For your specific dump, the most actionable interpretation is: the controller raised an automatic calibration error ( ACE ) during training, and DDRv’s write-leveling search could not find a valid operating region by adjusting WRLVL_START . That points first to reset/clock/configuration/DQ-map/SI checks, with DDR reset and DQn_MAP high on the list because both are repeatedly tied to this exact DDRv failure class in NXP debug history. So, verify DDR clock/RCW, DDR reset timing, SPD-derived rank/geometry, DQ mapping, and power/SI before tuning margins.

Regards