POR Status Register 1, How to set RSP_DIS bit

[benoitmasse]

Hi,

LS2044A

We want to use ASLEEP/GPIO1_28 as an output pin. But in the documentation, section 4.9.5 Power-On Reset Sequence Detailed Description, the ASLEEP signal is enabled if CFG_RSP_DIS=0.

The CFG_RSP_DIS's value is defined in section 8.3.2 POR Status Register 1 (PORSR1).

But I cannot figure out which pin will enable or disable RSP_DIS bit at POR.

And I have the same question for PORSR1's SOC bit.

My question is: How I can select RSP_DIS and SOC bits in PORSR1 ?

Thanks

[benoitmasse]

Ok, 

If I understand well, I do not have any restriction to use GPIO1_28. The ASLEEP will not be driven as output before RCW loading.

Reference Table 4.6 Reference Manual (09/2020) Stage 10, 

The ASLEEP pin is also enabled at this point if the Reset Sequence Pause is enabled
(CFG_RSP_DIS=0); otherwise ASLEEP pin is enabled later in the reset sequence.

Does not apply in my case.

Is it right ?

[ufedor]

This is an internal factory-test config signal that we don't support for customers’ use and, most importantly, that customers do not need to use/tweak for proper operation of the device.

As such, we'll pursue removing references to the signal name from the docs going forward.