PMU IRQ

[nitesh-einfochips]

I need to implement generation of an IRQ on overflow of a counter on 1046a . ARMv8 manual recommends using PPI 23 for this IRQ, but allows for board designers to use a different input. I wasn't able to find an explicit mention of the wiring of the PMUIRQ in LS1046A reference manual. Is there a specific  IRQ number  which I should be using when there is a counter overflow?

@igorpadykov @yipingwang 

[yipingwang]

Please check the table 5-1

Below information for PMU IRQ line is mentioned.

138 A72 core 0 PMU IRQ

139 A72 core 1 PMU IRQ

127 A72 core 2 PMU IRQ

129 A72 core 3 PMU IRQ

[nitesh-einfochips]

Do you have a sample example of how I can configure PMU interrupt when there is an overflow? @yipingwang

[nitesh-einfochips]

@yipingwang @Yuri I am looking into reference manual, and I can see I have to enable following regsiters
Select counter PMSELR_EL0, Select Event type PMXEVTYPER_EL0, setting interrupt PMINTENSET_EL1, start counter PMCNTENSET_EL0, write value to event counter PMXEVCNTR_EL0. I can see overflow getting generated by checking PMOVSCLR_EL0 register but I don't see interrupt getting generated. I am working on armv8.

[yipingwang]

What is the value of PMCR_EL0 ?

[nitesh-einfochips]

@yipingwang Thanks for the prompt response. The PMCR_EL0 value when read before writing is Default Value) 0x41023000 after enabling PMU the value is 0x41023001. I am writing 0x01 to enable PMU.

[yipingwang]

As you explained, your setting looks fine to generate the PMU interrupt. Can you share the values of all registers you have set as well. Meanwhile we will try to replicate the same at our end.

[nitesh-einfochips]

Do you have a sample example of how I can configure PMU interrupt when there is an overflow?