I updated the rcw_1000_sdboot.rcw file (below) to add missing and different value corrections. and got what appears to be a sane
rcw_1000_sdboot.bin file
/tmp/work/ls1021aiot-fsl-linux-gnueabi/rcw/git-r0/git/ls1021aiot/SSR_PPN_20> ls
rcw_1000.bin rcw_1000_lpuart.rcw rcw_1000_qspiboot.rcw rcw_1000.rcw rcw_1000_sben.rcw rcw_1000_sdboot.rcw rcw_1000_usb2.rcw
rcw_1000_lpuart.bin rcw_1000_qspiboot.bin rcw_1000_qspiboot_swap.bin rcw_1000_sben.bin rcw_1000_sdboot.bin rcw_1000_usb2.bin
wanderson@curly:/opt/nxp/QorIQ-SDK-V1.7/Freescale-Linux-SDK-for-LS1021A-IOT-Rev2-v0.4-20150907-yocto.iso/build_ls1021aiot_release/tmp/work/ls1021aiot-fsl-linux-gnueabi/rcw/git-r0/git/ls1021aiot/SSR_PPN_20> hexdump -x rcw_1000_sdboot.bin
0000000 55aa 55aa ee01 0001 0806 0a00 0000 0000
0000010 0000 0000 0000 0000 0020 0000 4008 0079
0000020 0260 005a 0421 0060 0000 0000 0000 0000
0000030 0000 0000 0320 0080 0220 0048 1b84 4013
0000040 0000 0000 0000 0000 5709 0002 ffff ffff
0000050 ee09 0002 1060 0000 6108 4000 c054 686d
0000060
If I proceed to rebuild u-boot using
bitbake -c cleansstate u-boot-ls1
bitbake -c clean u-boot-ls1
bitbake -c patch u-boot-ls1 2>&1 > p.out
bitbake u-boot-ls1 2>&1 > b.out
I notice the rcw directory <tmp>/deploy/images/ls1021aiot/rcw/ls1021aiot/SSR_PPN_20 contains my modified rcw_1000_sdboot.bin
but that the u-boot-ls1021aiot-2014.07-r0.bin created still has old RCW info. Did I miss a step.
Thanks again
Bill
modified ls102aiot/rcw_1000_sdboot.rcw file:
/*
* LS1021AIOT RCW for SerDes Protocol 0x20
*
* 3G configuration -- 1 RGMII + 2 SGMII
*
* Frequencies:
*
* Sys Clock: 100 MHz
* DDR_Refclock: 100 MHz
* SDREFCLK_FSEL: 100 MHz
*
* Core -- 1000 MHz (Mul 10 )
* Platform - 300 MHz (Mul 3)
* DDR -- 800 MHz (Mul 8)
* SGMII -- 125MHz
* PCIE -- 100MHz
*
* Serdes Lanes information
* A PCIe*1
* B SGMII1
* C PCIe*1
* D SGMII2
*
* Boot from SD card.
*
*/
#include <../ls1021aqds/ls1021a.rcwi>
SYS_PLL_RAT=3
MEM_PLL_RAT=8
CGA_PLL1_RAT=10
SRDS_PRTCL_S1=32
SRDS_PLL_PD_S1=1
SRDS_DIV_PEX=1
USB3_REFCLK_SEL=2
USB3_CLK_FSEL=57
A7_ACE_CLKDIV=2
A7_DBG_CLKDIV=2
HWA_CGA_M1_CLK_SEL=1
PBI_SRC=6
DP_DIV=1
OCN_DIV=1
IFC_MODE=37
/*IFC_MODE=64 Modified to match what I saw in iot factory image*/
DRAM_LAT=1
SYS_PLL_SPD=1
UART_BASE=7
IFC_GRP_E1_EXT=1
/*IFC_GRP_E1_EXT=4 orig */
EC1=4
/*EC2=2 changed to enable GPIO3[15:27]*/
EC2=1
QE-TDMA=6
QE-TDMB=6
SDHC=0
DVDD_VSEL=2
LVDD_VSEL=1
EVDD_VSEL=2
BVDD_VSEL=2
/* ADD */
UART_EXT=4
IFC_GRP_A_EXT=1
IFC_GRP_F_EXT=1
IFC_GRP_G_EXT=1
#include <../ls1021aqds/scfg_bit_reverse.rcw>
#include <../ls1021aqds/uboot_address.rcw>
~