LX2160 PCIe Endpoint Interrupts

[klaus_fiedler]

PCI-Express only supports MSI interrupts to be sent from Endpoint to Root Complex.

I would like to "send interrupts" to a PCI Endpoint using some non-standard methods like exposing the interrupt controller's registers to a PCI BAR. This BAR can then be accessed by another Endpoint to raise an interrupt.

Is this possible using the LX2160? (in particular, is it possible to expose the neccessary GIC registers to a PCI EP BAR?) 

Are there any examples how this can be achieved?

Are there other methods to signal interrupts to a LX2160 PCI Endpoint?

The Reference Manual provides some information about a "Mailbox" in the PCI chapter but no examples how this can be used. Is this another possibility for the use-case I described above?

[yipingwang]

As you mentioned correctly - PCI Express only supports MSI interrupts from EP to RC per the PCIe base spec.

Which section of PCIe chapter shows "Mailbox"? What is the LX2 RM revision?

I hope the question is on LX2160, Rev. 2 silicon. Please confirm?

[TrinathK]

Hi @yipingwang

I am looking for the same thing. I am using two custom LS1046 boards, one as RC and other as EP. I am able to generate MSI interrupt from EP to RC (Referred pci_endpoint_test.c) but i want to generate MSI interrupt from RC to EP. As per your reply, i understood that it is not possible. Please confirm and comment on it.

Thanks.

[klaus_fiedler]

The Mailboxes are described in chapter 22.5.1.7 Mailbox in "QorIQ LX2160A Reference Manual, Rev. D, 04/2019".

The revision of the silicon doesn't matter currently. This question shall clarify if we can use the LX2160 in our project in future. If it turns out that we can use the LX2160, we would of course use the latest available revision.

Can you also check if it is ok to map the GITS_TRANSLATER to a PCI BAR to raise interrupts from other PCI participants on the LX2160?

[yipingwang]

I would suggest referring to the latest device reference manual - LX2160ARM, Rev E.

The revision has new PCI-Express chapter for LX2160A silicon revision 2.0

It appears to me that you like to configure LX2160A as PCIe Endpoint and like to know any method to signal MSI to a LX2160 PCIe Endpoint (EP)?

You may not be concerned about LX2160A PCIe Root complex as RC can simply make Memory write (MWr) transaction to EP's inbound window to cause MSI.

[klaus_fiedler]

"It appears to me that you like to configure LX2160A as PCIe Endpoint and like to know any method to signal MSI to a LX2160 PCIe Endpoint (EP)?"

Exactly!

I already know that one possible solution might be to map to GITS_TRANSLATER to the Endpoint's BAR to be able to cause an interrupt by sending 32 bit of data to the Endpoint.

But I am not sure if this is working with the LX2160 (if the BAR can be really mapped to the GITS_TRANSLATER block and if the GITS_TRANSLATER block is able to receive the write from the BAR).

Could you please check if this is possible and if there are any bad side effects?

It would also be good to know if there are other possibilities  which are similar to the method I mentioned.

[yipingwang]

Software team's observation is that the implementation is complex.

It would be a a paid-service ticket for software team since the feature requested is outside the scope of PCIe base spec’s definition. I don’t think we can have an easy way to answer the question for Layerscape SoCs.

This include confirming the behavior of PCIe controller's LUT in EP mode. Most of the effort is the EP side works. LUT need to map the PCIe request to a streamID when this request is from RC to EP via EP’s bar.

If it all possible, software team need to check MSIx service on EP side.

On EP side:

1. EP hack the MSI driver to request a number of MSI interrupt based on a streamID and store the interrupt’s addr/data to a barA memory.
2. EP setup a LUT to map PCIe request ID to the streamID.
3. EP setup a barB to map GITS_TRANSLATER

On RC side:

4. Map the barB to access GITS_TRANSLATER
5. Map the barA to get the interrupt’s address and data
6. Write the data to the address to trigger a MSI interrupt via barB.

The proposal is to leverage the GICv3 ITS platform MSI driver. It should work, though we’d never used it.