LS1088A DDR4 validation problem

[PLeon]

Please clarify very specific question:

Our PCB design contains swapping of bits within a byte of static DDR4. We saw the requirement is to swap only within a nibble, but NXP support mentioned that it is not important.
What is the impact of swapping bits between nibbles?

Rem. The DDR initialization passes up to loading images (the D_INIT is OK). We can write and read kilobytes of data correctly, but some kilobytes are read not correctly.
The CW validation process fails on calibration.

[Hector_Villarruel]

Hello @PLeon 

Hope this post finds you well,

You inform us that the CodeWarrior Calibration has failed.

Could you please be so kind to provide us with your CodeWarrior logs?

Do you have any specific error?

We will be aware for your kind reply.

Have a great day.

BR,

Hector Villarruel 

[PLeon]

Thank you! Please, find attached the logs.

BUT, PLEASE, ANSWER THE MAIN QUESTION!!!

IS IT OK TO SWAP BITS BETWEEN(!!!) NIBBLES!!!

[Hector_Villarruel]

Hello @PLeon 

Hope this post finds you well,

Based on your last update,

Answering your question:

I recommend you to follow the appropriate guidelines in your PCB design, 

Kindly refer to the Table 1. DDR4 design checklist from AN5097 Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces Rev. 3 — 26 July 2023

Ensure bit and byte swapping rules are applied:
• Byte-swap is allowed in any order that would best fit the customer's design.
• No specific byte ordering is enforced or required.
• Bit-swap is only allowed within a nibble.
• Bit-swap across two nibbles is not allowed.
• Bit-swap across byte lanes is not allowed.
• Swapping of nibbles within a byte lane is allowed.
• When DDR4 Discrete DRAM is soldered on the board and two chip selects are
used, and the second chip select is bit swizzling[1], then bitmap orders of 0x10 (2 1
3 0) and 0x30 (6 5 7 4) are not allowed.
• For a 32-bit or 16-bit DDR4 data bus, the bit 0 (DQ[0]) and bit 1 (DQ[1]) of an ECC
byte lane, bit-swap is not allowed.

Have a great day.

BR,

Hector Villarruel

[PLeon]

Dear Hector,

Beleive me that we studied all the possible notes, internet articles and other sources during these 3 months we are struggling with the problem.

We want to be sure that swapping between nibbles is the answer to our DDR4 problem (Otherwise all effort of changing the PCB costing thousand of dollars will not solve the problem), although Mark Haddad and Michel Beckle:

1. We have attached the Code warrior configuration tool  generated ddr_init1.c file. One can see that dq_map[3..0] registers not used for CONFIG_STATIC_DDR (see attached file).

Why do you say is should be done !!!! Please explain how swapping between nibbles is noticed by NXP DDR4 controller if CRC write command is not used ?

2. CPU LS1088A DDR4 controller does not support write CRC command (verified with NXP support), this means that swapping within byte should work !!

PLEASE, answer these specific questions.

[Hector_Villarruel]

Hello @PLeon 

Hope this email finds you well,

I would like to ask you, are Mark Haddad and Michel Beckle involved on this situation?

Do you have a Paid Support Services ?

Have a great day.

BR,

Hector Villarruel S

[PLeon]

Hello, Hector.

No, we do not have paid support.

Marc and Michele took part in the first phone conversation when we asked for support and they stated that swizzling between(! not within) nibbles will work.
And as we can't make DDR4 to work we again return to this question also because we see in the documentation that it will not work.

So, where is the truth?