LS1088 Single source clocking and DDRCLK

[mcbridematt]

For the LS1088, as with other LS10xx SoC's, I understand DIFF_SYSCLK can be used as a replacement for the single-source SYSCLK and DDRCLK, as well as (1088 only), for SerDes PLL.

However, AN5144 (LS1088 design checklist) notes that DDRCLK 'This pin must always be connected to a 66.7-133.3 MHz input clock.'.

Is this a typo?

Can I use DIFF_SYSCLK only and pull down DDRCLK to GND, as I can with SYSCLK?

[ufedor]

I believe that the Checklist recommendation is connected with the fact that hard-coded RCWs select DDRCLK as DDR PLL source clock. Initial board bring-up could be more complicated if DDRCLK is not applied.