LS1046A serdes backplane eth driver & device tree questions

[Anuz]

Hi there,

I am trying to make three backplane ethernet drivers work on one our board based on ls1046a.

Serdes 1 have two devices

1. 10GBase-KR connected on lane 0(or Lane D) SD1_RX0_P/N & SD1_TX0_P/N XFI.9

2. 10GBase-KR connected on lane 1(or Lane C) SD1_RX1_P/N & SD1_TX1_P/N XFI.10

Serdes 2 have one device:

1. 1000Base-KX on lane (or Lane B) SD2_RX1_P/N & SD2_RX1_P/N SGMII.2

This can be found in LS1046ARM reference manual section 31.1.2 (page 1915 onwards)

In order to make these devices work I got backplane drivers from https://source.codeaurora.org/external/qoriq/qoriq-components/linux-extras/

Also I start referring to Application note AN12572 Ethernet Backplane Driver Support

Now according this note you need to create entry for each serdes node in dtsi common file,

which is given as

serdes1: serdes@1ea0000 {
compatible = "fsl,serdes-10g";
reg = <0x0 0x1ea0000 0 0x00002000>;
fsl,lane-reg = <0x9C0 0x980 0x940 0x900 0x8C0 0x880 0x840 0x800>;
/* lanes H, G, F, E, D, C, B, A */
little-endian;
};

So my first question is

Q1. Is there a reason this node is serdes1 and not serdes0, by linux convention, I would have assumed that node numbering should begin at 0 and not 1?

Q2. For drivers, there are two compatible properties, "fsl,serdes-10g" and "fsl,serdes-28g", I am guessing I have to use "fsl,serdes-10g" for first wo devices and for third device I would still use "fsl,serdes-10g" but supply "backplane-mode" as "1000base-kx" for 1000base-kx device.

Q3. "fsl,lane-reg" reg property is supplied with some offset values for each lane, in ls1046arm manual I can't find offset for these lanes, there are offset for various registers, but I am not sure how register offsets are related to lane addresses? SDn_TX/MXm_P/N do not seem have any offset values in the manual? (n=0,1& m=0,1,2,3)

Q4.According to app note "the correct endianness must be specified to allow access dependent on target endianness", for serdes node, I am assuming target is pcs_mdio nodes, I can't find what endianess apply to them, however according to CCSR memory map(table 2.4, page 150):

1EA_0000 - 1EA_FFFF SerDes Control 1 Big-endian (byte swapping
required)
1EB_0000 - 1EB_FFFF SerDes Control 2 Big-endian (byte swapping
required)

Serdes itself is big endian and all DPAA components are big endian as well, so the value for serdes node and pcs node be big endian?

Q5. For phy device nodes under mdio, how do I determine "reg" and "fsl,lane-reg" values

&mdio2 {
pcsphy1: ethernet-phy@0 {
 backplane-mode = "1000base-kx";
 compatible = "ethernet-phy-ieee802.3-c22";
 reg = <0x0>;
 fsl,lane-handle = <&serdes2>;
 fsl,lane-reg = <0x840 0x40>; /* lane B */
 };
+};

Q7: In file arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts, which is file we are using as base for our board, there is a node :

ethernet@1 {
compatible = "fsl,dpa-ethernet-init";
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
};

How do I get these values for "fsl,qman-frame-queues-rx" & "fsl,qman-frame-queues-tx", which would be relevant to ethernet we need to add?

Q8. Do I need to compile fsl_backplane_serdes_28g.o at all for these drivers to work?

Q9. Similarly, can also I compile without CONFIG_FSL_BACKPLANE_DEBUGFS & CONFIG_FSL_BACKPLANE_DEBUG_MONITORING for these drivers to work?

Thank you

[stadium_aquino]

I'm not NXP support, but here are some quick answers:

A1: (presumably) It follows the documentation to keep the engineers sane.

A2: Yes

A3: It's the offset of GCR0 for that lane. Note that for the LS1046A, lane 0 (aka the pins) is lane D (aka the registers)

A4: MDIO devices do not have endianness. The endianness specification is for the serdes.

A5: The reg should match MDEV_PORT from the protocol control register. It resets to 0 and I have never seen it changed.

A8: No

A9: Yes

[Anuz]

Thanks for  your answer.

Now I can atleast see 10G working on Linux.

Though I still have not been able to make 1G work, I feel like drivers for 1G either do not exist or there needs to be more to be done for 1G.

Similar to this, how can I make 10G backplane work on uboot? Is there a similar driver for uboot?

Another question, which is related to lane reset procedure.

Following registers needs to be updated

LNmGCR1[REIDL_TH]
• LNmGCR1[REIDL_EX_SEL]
• LNmGCR1[REIDL_ET_MSB]
• LNmTECR0[AMP_RED]

My understanding is LNmGCR1 corresponds to serdes2 and LNmGCR0 corresponds to serdes1?

But then there is only one  set of TECR  registers LNmTECR0, there is no LNmTECR1? Changing this value should affect which serdes 1 or 2?

[stadium_aquino]

> Similar to this, how can I make 10G backplane work on uboot? Is there a similar driver for uboot?

AFAIK no. I think it's unlikely that there will ever be a 10G driver because of the complex link training sequence. You could probably write up a KX driver, but one does not exist yet.

> My understanding is LNmGCR1 corresponds to serdes2 and LNmGCR0 corresponds to serdes1?

No. Both those registers are present on the same serdes. For example, LNAGCR0 on serdes 1 would have address 0x1ea0800, and LNAGCR1 on the same serdes would have address 0x1ea0804.