LS1046A address spaces

[AngelMorales]

Hi all,

I am starting to use LS1046ARDB board and getting used to CodeWarrior debugging. I have always considered the address map (40-bit addresses) at LS1046ARM. However, I am not sure if this is the same address space that is "seen" by the software since it has 64-bit ARM cores. Is it necessary some 'translation' between 64-bit and 40-bit address spaces?

Thank you and best regards.

[ufedor]

> I did have another question about the translation from 48-bit core physical address

> to the 40-bit local address space: is it performed by using only the 40 least

> significant bits of the core physical address?

Please refer to the ARM® Cortex®-A72 MPCore Processor Revision: r0p2 Technical Reference Manual, Chapter 5 Memory Management Unit.

In case of further questions please apply to the ARM Technical Support directly.

[ufedor]

The ARM Cortex A72 support 48-bit physical addressing, but the CCI-400 only supports 40-bit addressing, so the Local Address Space is constrained to 40 bits.
The virtualization and address translation process is explained at length in the ARM AARCHv8 reference manual. The process is divided into stage 1 and stage 2 translation, where stage 1 translation means translating Virtual Address (VA) to Intermediate Physical Address (IPA, also referenced to as Guest Physical Address), while stage 2 translation means translating IPA to Physical Address (PA). The purpose of separating the process into 2 stages is to allow the guest OS to control the address translation between VA and what it “thinks” is the PA, while the Hypervisor controls the translation from IPA to PA. This split process allows the Hypervisor to separate the resources of different Virtual Machines (VMs). Address translation is performed both in the cores and also for IO devices, using the System Memory Management Unit (SMMU). SMMU architecture is described in ARM’s System MMU architecture specification.