[LS1046A] RGMII TX clock has incorrect frequency (5MHz)

[lukasz_laguna]

Hello. We are bringing up the custom board based on the NXP LS1046A and we have a problem to get successful ping using RGMII interfaces (TI DP83867 PHY):

```
=> ping 192.168.4.1
Using FM1@DTSEC3 device

ARP Retry count exceeded; starting again
ping failed; host 192.168.4.1 is not alive
```

PHYs are connected as 100Mb (SGMII connected as 1Gb with the same PHYs works fine).

We are debugging it on really low level using oscilloscope. Comparing the signals to the signals from the reference platform LS1046ARDB, we currently have the correct signals on RX_Data and RX_Clock lines (proper CLK frequency 25MHz, proper skew between data signals and clk signal), but the ping still fails, so we started examination of the TX lines and it turned out that TXC signal frequency is equal to 5MHz and we think this is the last problem, which blocks us from getting successful ping.

From what we were able to observe, SPEED_100 is selected in fm/memac.c driver.

Maybe you have an idea what can be wrong (PLLs configuration, MAC configuration?) and what can we do to fix this problem?

Thanks.

[ufedor]

1) What are measured clock frequencies at EC1_GTX_CLK125 and EC2_GTX_CLK125?

2) What is the SCFG_ECGTXCMCR[CLK_SEL] value?

Please ensure that frequency of the ECn_GTX_CLK125 selected by the SCFG_ECGTXCMCR[CLK_SEL] must be 125MHz.

[lukasz_laguna]

ufedor thank you for the answer. You were right, it was a good place to look for
the issue.

The frequencies of EC1_GTX_CLK125 and EC2_GTX_CLK125 signals are 25MHz.
Could you please confirm that this is strictly required that the CLK provided
to those is 125MHz, even if we want to use RGMII at 100Mbit only?

The description we found in the reference manual was:

RGMII transmit 125 MHz source.
This signal must be generated externally with a crystal or oscillator, or is sometimes provided by
the PHY.

We suppose that in the 100Mbps mode the GTX_CLK125 is divided by 5 in order to
get 25MHz on TXC. Since we provide 25MHz there, not the 125MHz, we are getting
5MHz as a result. We are wondering whether there is some workaround to be
done on a firmware level to disable / change the frequency divider in
order to test the RGMII interface further.

As far we can see, the TI PHY we are working with is not able to output
the 125MHz on CLKOUT pin when 100Mbit is used.

[ufedor]

125 MHz is the only option for the GTX_CLK125. It doesn't depend on the transfer rate.

[lukasz_laguna]

ufedor, thank you for your help. We made a little hardware rework and it solved the problem.

[rahul_bhagat]

Hello Lukas,

How to solve the problem? Have you used crystal oscillator for  ECn_GTX_125 signal for RGMII interface?

Best regards,

Rahul