LS1046A QSPI_CLK on boot glitches

[jvbentley93]

Hello,

We are trying to bring up a custom LS1046A board.

We are trying to boot off of a QSPI NOR Flash device.

The CFG_RCW_SRC[0:8] strapping resistors are set to: 0_0100_0100

We have already verified that POR_N and power supply sequencing is correct.

When we apply power to the device, after supplies come up and we de-assert  POR_N after minimum hold time we see CS_N go low for about 100microseconds. During that time the QSPI CLK starts sending random ticks on the line.

For example, we might see two cycles of expected period, then two cycles where the CLK stays high, then a few more regular cycles, and then several missed cycles where it stays low. Every time we reset the board and probe the QSPI CLK there appears to be random behavior on the line.

Is there any known errata for this?

[Oswalag]

Hello,

You can submit a new technical case and ask for the errata documentation as it is available only under NDA.