LS1046A Clock Questions

[smiller2]

I am trying to configure the RCW for a new design.    I copied the clock scheme from the LS1046ARDB-PB.   That seems to have a single-ended SYSCLK set to 80MHZ.   The differential SYSCLK is at 100MHZ.     The FRWY board has the single-ended SYSCLK and the differential SYSCLK running at 100MHZ.

When I start up a new QorIQ Configuration Project in Code Warrior, the default SYSCLK is 66.67MHZ and the default differential SYSCLK is 100MHZ.    Which of these is used during the boot?    Is there a RCW bit that determines the source?     Is there a benefit of having the single-ended SYSCLK at a slower frequency?    Should I dial back my board back to 66.67MHZ? 

Thanks.

[smiller2]

OK,  I found my problem.    The switch between the single-ended clock and the differential clock is controlled by the "IFC_WE0_B"  pin.     Since this pin is part of the IFC bus which I am not planning on using,  I just tied it high in my schematic.   That is a mistake!    As that would force me into single ended clock mode only, unless it can be overwritten after the RCW is loaded. 

I strongly recommend App Note AN5252 as it has much more information about the clock modes than any of the datasheets.   Refer to section 5.30.

[Bulat]

You are right, IFC_WE0 defines which SYCLK option will be used as a system clock. This selection can not be changed/overwritten later.

Even if you select single-end SYSCLK by chance, DIFF_SYSCLK can still be used to clock DDR interface (RCW option) and/or USB PHYs (SCFG_USB_REFCLK_SELCRn registers, default setting).