LS1046A CGA_PLL frequency

[GyM]

The LS1046A datasheet, section 5.1 lists the "Core cluster group PLL frequency" minimum of 1000 MHz. This is confusing: Is this the CGA_PLL1 and CGA_PLL2 minimum frequency of operation or is it the CoreClock minimum frequency? 

This should be specified as two separate lines: one for the CGA_PLL min/max frequency, the other for the Coreclock min/max frequency.

[mrudangshelat-13]

Hi @GyM,

Refer to figure 4-5 mentioned in the LS1046A reference manual. The 1000MHz is the minimum frequency that must be provide to the core cluster. And CGA_PLL1/2 is used to generate that frequency from the SYSCLK which is provided externally. You need configure the CGA_PLL1/2 in RCW and its details is mentioned in table 4-14 (pg# 219, 220).

Regards,
Mrudang

[GyM]

Hi @mrudangshelat-13 

Thanks for the answer but it does not completely answer my question.

The 1000 MHz is the minimum frequency for the core cluster, I understand this.

Let's say that I use CGA_PLL1 to provide this frequency to the core cluster. What are the frequency limits for CGA_PLL2 which could be used for QSPI for example? If SYSCLK is 100 MHz (typical value), and the lowest ratio for CGA_PLL2_RAT is 5:1 and the highest ratio is 40:1, this would mean I could configure CGA_PLL2  to operate between 500 MHz and 4000 MHz ?

Normally a PLL has a valid range of operation, this should be specified separately, in the data sheet, from the core cluster frequency range.

Regards,

GyM

[mrudangshelat-13]

Hi @GyM,

The PLL can be configured to the value mentioned in the reference manual. There is no such limit apart from that. It is just that you need to configure the PLL as per your requirement. For example, if the limit of core cluster is 1000MHz to 1200MHz, then it becomes the limitation of the PLL.

Regards,
Mrudang

[GyM]

Hi @mrudangshelat-13 

In the RCW, C1_PLL_SEL can be selected to be CGA_PLL1 /2. So to limit the Core cluster from 1000 MHz to 1200 MHz, the the CGA_PLL1 frequency would have to be between 2000 MHz and 2400 MHz, Right? If yes, then the PLL limits are NOT the same as the core cluster frequency limits!

Also you totally avoid the question of the second PLL, for example CGA_PLL2, which in my example is not providing the core cluster frequency.

Refer to Note 1 of Table 140 of the datasheet:

1. Caution: The platform clock to SYSCLK ratio and core to SYSCLK ratio settings must be chosen such that the resulting SYSCLK frequency, core frequency, and platform clock frequency do not exceed their respective maximum or minimum operating frequencies.

This corresponds to what you are saying and it is correct from an operational point of view. The user has to make sure the settings respect the limits for the core cluster frequency, etc.

But it does not say anything about if there are other physical or electrical limits to the PLL frequency limits by it self.

[mrudangshelat-13]

Hi @GyM,

It is not necessary for the CGA_PLL1 frequency to be between 2000 MHz and 2400 MHz as there is CGA_PLL1 /1 option available in C1_PLL_SEL (RCW:96-99). Refer to figure 4-5 for better understanding of the flow of the system

You can configure the CGA_PLL2 based on your requirement using CGA_PLL2_RAT, HWA_CGA_M2_CLK_SEL & SCFG_QSPI_CFG[CLK_SEL]. If you need more clarification then you can check the FRWY-LS1046A reference board.

Again, the PLL can be configured as per the setting available in the reference manual. But you need to take care that the PLL is configured according to the system requirements like the core cluster.

Regards,
Mrudang

[GyM]

Hi @mrudangshelat-13 

Let's take a different approach with a concrete example:

We have SYSCLK = 100 MHz.  If we select RCW(C1_PLL_SEL) = 0000 CGA_PLL1 /1 and CGA_PLL1_RAT = 00_1100 12:1 Async, then we get the Core Clock frequency of 1200 MHz which meets the limits above. For FMAN, we can put HWA_CGA_M1_CLK_SEL = 010 to get a frequency of 600 MHz. These settings match the system requirements in the datasheet and the reference manual for the Core cluster and MFAN frequencies.

Since CGA_PLL2 is not used for either the Core Cluster clock or the FMAN clock, can we configure the CGA_PLL2_RAT = 00_0101 5:1 Async to get a PLL2 frequency of 500 MHz and get a lower QSPI/eSDHC speed after the RCW? Or does the CGA_PLL2 output frequency also have to be at a minimum of 1000 MHz?

[sanspepin]

Hi

Similar question with ls1046a. What is the min/max Fman clock frequency? I saw some board configuring the Fman to 500MHz or 900MHz. How to choose the proper Fman clock?

[mrudangshelat-13 · Accepted solution]

Hi @GyM,

As you are using CGA_PLL1 for core cluster, the CGA_PLL2 will be independent from the limitations of core cluster. You can configure it as per the available range mentioned in the reference manual.

Regards,
Mrudang