LS1046A Boot process

[TrinathK]

Hi all,

I need clarification on the below mentioned points, to finalize our schematic design (using LS1046A board design).

1. We boot from QSPI NOR Flash or eMMC or Micro SD and boot device selection switches (or DIP switches) are interfaced to CPLD, from where the processor reads the boot device information depending on the switch selection. Let me know,

a) How BIOS searches for a bootable device after power-on ?

b) Is there any boot priority for that and can we modify it ?

c) What is the default boot device ?

d) Who will perform device initializations for the selected boot device ?

e) What are the responsibilities of first stage and second stage bootloaders in this regard. Is it possible to customize bootloader settings and its source code ?

2. In our current design, CMSIS-DAP is not available, Is it possible to load my firmware, u-boot, kernel and root file system using JTAG (i.e., without using Code warrior tap) ?

3. How to add user defined console port (terminal) on a target board ? Who will perform initializations for that port ?

Thanks in advance.

[arm_linux]

mark，I am find yipingwang he is a great man

[TrinathK]

Hi Yipingwang,

 I have done that already. I compiled ATF, RCW, U-BOOT and everything is working fine. Now i am trying to change console port to UART2, so let me know, where should i change that setting in source code.

Also please answer point no 2. [At power on, what is the interface between CPLD and processor for reading cfg_rcw_src[0:8] -> IFC or GPIO ? ]

Thanks again.

[yipingwang]

Please create new threads for your new questions.

[TrinathK]

Hi Yipingwang,

Thanks for your reply. I have already gone through "power on sequence" and nxp documentation (bootloader section). I have some queries regarding this.

1) Where these PBL/PBI (Pre-Bootloader/Pre-Boot Initialization) commands are present ? Please provide documentation.

2) At power on, what type of interface is present between CPLD and processor for reading cfg_rcw_src[0:8] -> IFC commands or GPIO ? (i.e., For booting, can i hardwire cfg_rcw_src[0:8] without using CPLD ?).

[yipingwang]

1. You could download the latest LSDK 21.08, then execute the following commands to get RCW/PBL/PBI in folder components/firmware/rcw/ls1046ardb/RR_FFSSPPPH_1133_5559/rcw_1600_qspiboot.rcw.

$ flex-builder -c rcw -m ls1046ardb

2. Please refer to "LS1046A Reference Design Board Reference Manual“

downloaded from https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1046a-reference-design-board:LS104....

You could use hard-coded RCW on the target board. 

[yipingwang]

Please refer to "4.4.1 Power-on reset sequence" in LS1046 reference manual.

You need to configure RCW for the boot source.

No default boot device.

ATF/u-boot will perform device initialization.

TF-A boot flow
1. BootROM (BL1)
a. When the CPU is released from reset, hardware executes PBL commands that copy the BL2 binary (bl2.bin)
for platform initialization to OCRAM. The PBI commands also populate the BOOTLOC ptr to the location where
bl2.bin is copied.
b. Upon successful execution of the PBI commands, Boot ROM passes control to the BL2 image at EL3.
2. BL2
a. BL2 initializes the DRAM, configures TZASC
b. BL2 validates BL31, BL32, and BL33 images to the DDR memory after validating these images. BL31, BL32, and
BL33 images form FIP image, fip.bin.
c. Post validation of all the components of the FIP image, BL2 passes execution control to the EL3 runtime firmware
image named as “BL31”,
3. BL31
a. Sets up exception vector table at EL3
b. Configures security related settings (TZPC)
c. Provides services to both bootloader and operating system, such as controlling core power state and bringing
additional cores out of reset
d. [Optional] Passes execution control to Trusted OS (OP-TEE) image, BL32, if BL32 image is present.

You could modify atf and u-boot source code for your customize board.

CMSIS-DAP is not available, you could deploy SD boot or prepare CodeWarrior TAP to connect to JTAG to program QSPI flash.

ATF/u-boot will initialize the serial port.