LS1046 bringup stuck in BL2, DDR init failed

[SimonRo]

We have a custom LS1046 board with DDR4. I have mapped DQ lines and got a successful CodeWarrior DDR validation and passed Operational DDR tests with ECC disabled, and speed 1300 MT/s. I have 4 x 1Gb x 16 DDR4 devices fitted.

I've taken the ddr_init1.c output and applied it to my atf version lf-5.10.52-2.1.0.

BL2 fails to boot from SD Card (DDR init failed). If I use the ddr_raw_timing structure from Codewarrior (no CONFIG_STATIC_DDR) I get:

INFO: SoC workaround for Errata A008850 Early-Phase was applied
INFO: SoC workaround for Errata A010539 was applied
INFO: RCW BOOT SRC is SD/EMMC
INFO: SoC workaround for DDR Errata A008511 was applied
INFO: SoC workaround for DDR Errata A009803 was applied
INFO: SoC workaround for DDR Errata A009942 was applied
INFO: SoC workaround for DDR Errata A010165 was applied
INFO: time base 0 ms
NOTICE: Fixed DDR on board
INFO: Time after parsing SPD 4 ms
ERROR: Board parameters no match.
ERROR: Failed matching board timing.
ERROR: DDR Clk: MCLK cycle is 481 ps.
ERROR: DDR Clk is faster than DIMM can support.
ERROR: mclk 481 invalid
ERROR: cas latency is too large 42
ERROR: Calculating DDR registers failed
ERROR: Calculate register error
ERROR: DDR init failed.
INFO: SoC workaround for Errata A008850 Post-Phase was applied
INFO: RCW BOOT SRC is SD/EMMC
INFO: esdhc_emmc_init
INFO: Card detected successfully
INFO: init done:
NOTICE: Incorrect DRAM0 size is defined in platform_def.h
ERROR: mmap_add_region_check() failed. error -22
ERROR: mmap_add_region_check() failed. error -22
NOTICE: BL2: v2.4(release):lf-5.10.52-2.1.0-rc2-0-gbb4957067-dirty
NOTICE: BL2: Built : 14:21:46, Jan 16 2025
INFO: Configuring TrustZone Controller
INFO: BL2: Doing platform setup
INFO: BL2: Loading image id 3
INFO: sd-mmc read done.

If I define CONFIG_STATIC_DDR and use the static_1300 struct from Codewarrior I get:

INFO: SoC workaround for Errata A008850 Early-Phase was applied
INFO: SoC workaround for Errata A010539 was applied
INFO: RCW BOOT SRC is SD/EMMC
INFO: SoC workaround for DDR Errata A008511 was applied
INFO: SoC workaround for DDR Errata A009803 was applied
INFO: SoC workaround for DDR Errata A009942 was applied
INFO: SoC workaround for DDR Errata A010165 was applied
INFO: Time before programming controller 0 ms
WARNING: Warning: Optimal CPO value not set.
ERROR: Found training error(s): 0x3000
ERROR: Error: Waiting for D_INIT timeout.
ERROR: Writing DDR register(s) failed
ERROR: Programing DDRC error
ERROR: DDR init failed.
INFO: SoC workaround for Errata A008850 Post-Phase was applied
INFO: RCW BOOT SRC is SD/EMMC
INFO: esdhc_emmc_init
INFO: Card detected successfully
INFO: init done:
NOTICE: Incorrect DRAM0 size is defined in platform_def.h
ERROR: mmap_add_region_check() failed. error -22
ERROR: mmap_add_region_check() failed. error -22
NOTICE: BL2: v2.4(release):lf-5.10.52-2.1.0-rc2-0-gbb4957067-dirty
NOTICE: BL2: Built : 14:52:12, Jan 16 2025
INFO: Configuring TrustZone Controller
INFO: BL2: Doing platform setup
INFO: BL2: Loading image id 3
INFO: sd-mmc read done.

I can see DDR clock on a scope at 650MHz. I'm fairly confident on the DQ map as I've double checked, and DDR Validation passed.

Does anyone have any ideas what I should do next? 

Thanks

[yipingwang]

Please boot ATF on the target board, then connect CodeWarrior to the target board to create a QCVS DDR project with "From target" method, then check whether the generated DDR controller configuration parameters are same with what you provided in ATF source code.

[SimonRo]

When I do this should all properties match, e.g. does CodeWarrior get the DQ Mapping from the running board? 

I'm seeing a lot of difference in the DQ mapping for example.

[yipingwang · Accepted solution]

Yes, CodeWarrior gets the DQ Mapping from the running board.