LS1043A- RESET

[Sandra1405]

Hello NXP Team,

We would like your support in reviewing the reset implementation we designed for the LS1043A processor. (we are referring to reference design LFGTWSEM for reset implementation)

Kindly let us know if the below implementation works.

Please confirm, whether the RESET_RQ_n signal de-asserts after the assertion of the PRORESET_n signal. If the RESET_RQ_n signal is not deasserted immediately after the assertion of the PRORESET_n signal, the processor will not come out of reset.

We want to confirm that the processor will not go into a deadlock state by any means with this current implementation.

Please share your valuable review comments ASAP.

Thanks & Regards

Sandra

[JosephAtNXP]

Hi,

Thank you for your interest in NXP Semiconductor products,

I think that REQ signal shouldn't be delayed, according to the RM:

Asserted-An event has triggered a request for either a hard reset or a
power on reset.

So the request would be delayed.

Now RESET_REQ_B is used as a request to external reset logic that the processor needs to be reset. The processor generates RESET_REQ_B as a logic level 'low', not a pulse. This low level will be kept until external logic asserts PORESET_B or HRESET_B to the processor. These reset signals work as a handshake: RESET_REQ_B is negated after reset assertion. But have in mind that your circuit would have a request for a {delay} more, which would result in a undetermined situation, experimentation would be good but extracting that delay would be better.

Regards