LS1043A DDR4 Chip Select for 2-Rank Configuration

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LS1043A DDR4 Chip Select for 2-Rank Configuration

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jessh54
Contributor I

I am currently trying to integrate 16 GB of DDR4 with the LS1043A. I have selected a Micron 2Gbx8 discrete DRAM for the application that will be use four DRAM chips per rank with an additional ECC chip. There will be two ranks.

My question is in regards to the chip select connections. My understanding is that each rank would require an independent chip select (i.e. CS0 => Rank1, CS1 => Rank2). Figure 11 of the Reference Manual shows this type of connection. However, the LS1043A reference design uses two chip selects for its one and only rank. CS0 connects to the CS pin as expected, but CS1 connects to the C1/CS1_n of the Micron DRAM. CKE1 and ODT1 are also connected to the single-rank DRAM, where I would think that those would be  connected to Rank 2.

Why are both the CS, ODT, CKE [0] and [1] signals connected the the DRAM chips in a single rank configuration?

For the two rank configuration, would the CS, ODT, and CKE [0] signals connect to the DRAM of Rank1 and the CS, ODT, and CKE [1] signals all connect to Rank2? This seems logical to me, but I can't understand why two sets of signals are connected to one rank.

Does NXP have a reference design available showing more than one rank configuration that is available for me to study?

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ufedor
NXP TechSupport
NXP TechSupport

Your understanding is fully correct.

The LS1043ARDB schematics was prepared in assumption that twin-die DDD4 SDRAM devices can be used.

From the Micron Data Sheet:

"DDR4 will support a traditional DDP package, which uses these three signals for control of the second die (CS1_n, CKE1, ODT1)."

You wrote:

> For the two rank configuration, would the CS, ODT, and CKE [0] signals connect to the

> DRAM of Rank1 and the CS, ODT, and CKE [1] signals all connect to Rank2?

CS0, ODT0, CKE0 - rank 0 (1)

CS1, ODT1, CKE1 - rank 1 (2)

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ufedor
NXP TechSupport
NXP TechSupport

Your understanding is fully correct.

The LS1043ARDB schematics was prepared in assumption that twin-die DDD4 SDRAM devices can be used.

From the Micron Data Sheet:

"DDR4 will support a traditional DDP package, which uses these three signals for control of the second die (CS1_n, CKE1, ODT1)."

You wrote:

> For the two rank configuration, would the CS, ODT, and CKE [0] signals connect to the

> DRAM of Rank1 and the CS, ODT, and CKE [1] signals all connect to Rank2?

CS0, ODT0, CKE0 - rank 0 (1)

CS1, ODT1, CKE1 - rank 1 (2)

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jessh54
Contributor I

This is probably more of a question for Micron, but I figured I'd ask anyway in case you or anyone else knows.

When utilizing the single die DRAM, is it safe to leave the CS, ODT, CKE [1] signals un-connected? I found no mention of connection or termination for these pins in their data sheet.

I find it somewhat odd they would leave these pins and their pin descriptions in the data sheet for a single die DRAM.

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ufedor
NXP TechSupport
NXP TechSupport

> is it safe to leave the CS, ODT, CKE [1] signals un-connected?

Yes - refer to the AN5012 - QorIQ LS1043A Design Checklist.