I have a question regarding data-bit swap within byte-lan in combination with write levelling for the LS1043A
Does write level support mean the DQ0 pin cannot be swapped? Or is the functionality supported on all pins.
If memory device also matters, we plan to use: Micron MT41K512M16
It is possible to swap any bits within a byte lane. Please refer to the nxp appnote AN3940, Table 1. “DDR3 Designer Checklist”, No 45.