LS1043 CPLD READ

[carlos-m-ribeiro]

Good afternoon, we are using an u-boot for ls1043 in QSPI with our custom board but if we read from address 0x7fb00000 where we have our cpld, the value read is always 0xff:

=> md.b 0x7fb00000 1
7fb00000: ff .
=> md.b 0x7fb00000 1
7fb00000: ff .
=> md.b 0x7fb00000 2
7fb00000: ff ff

We verify all configurations and we did many tests since many weaks ago. If possible, with your experience, could you review quickly our IFC configurations in attached files.

Thank you

[ufedor]

Please provide additional information:

1) IFC to CPLD connection schematics as PDF

2) ".rcw" file being used

3) dump of the IFC CCSR registers in U-Boot

[carlos-m-ribeiro]

Hello,

Which section from ls1043a manual we can find the IFC CCSR registers?

Thank you

[ufedor]

25.3 IFC memory map/register definition

[carlos-m-ribeiro]

Hello, if NXP can review, we send now the IFC connections (see also the image) and the RCW file/binary.

IFC_A22 ... IFC_A25 -> DATA0 to DATA3
IFC_A16 -> QSPI_A_CS0
IFC_A18 -> QSPI_A_SCK

[ufedor]

In the provided "rcw_ac16_qspi.bin" RCW[IFC_MODE] is set to 0b001000100.

Please consider that in the QorIQ LS1043A Reference Manual, Table 4-9. RCW source encodings there is note 1 for cfg_rcw_src 0_0100_010x saying:

"Not valid as an RCW[IFC_MODE] encoding"

It is needed to correct the RCW[IFC_MODE] to contain a valid cfg_rcw_src value from the Table 4-9.

[carlos-m-ribeiro]

Ok, and which "cfg_rcw_src" valid value you suggest to boot from QSPI in ls1043a, using CPLD?

Best regards

[ufedor]

Have you tested CPLD access when booting from IFC Flash?

[carlos-m-ribeiro]

Hello, booting from NAND, the CPLD access is correct but if we booting from QSPI and use now "cfg_rcw_src" equal to 0b000100101 (the RCW word is 0x40025000) with the parameters in attached file, every read from 0x7fb00000 is 0x15.

[ufedor]

> booting from NAND, the CPLD access is correct

Set this mode (NAND) in the RCW[IFC_MODE] when booting from QSPI.

[carlos-m-ribeiro]

Ok, we will try "set this mode (NAND) in the RCW[IFC_MODE] when booting from QSPI". Before this, we also read the IFC registers:

IFC_CSPR:

=> md.l 0x1530010 1
01530010: 01010060 `...
=> md.l 0x153001c 1
0153001c: 8500b07f ....
=> md.l 0x1530028 1
01530028: 8500bf7f ....
=> md.l 0x1530034 1
01530034: 00000000 ....

IFC_CSOR:

=> md.l 0x1530130 1
01530130: 0c800000 ....
=> md.l 0x153013C 1
0153013c: 0c800000 ....
=> md.l 0x1530148 1
01530148: 0c000200 ....
=> md.l 0x1530154 1
01530154: 0c000000 ....

Thank you.

[carlos-m-ribeiro]

After "set this mode (NAND) in the RCW[IFC_MODE] when booting from QSPI (in u-boot-4-2020-LSDK-20.12)" the problem of read always 0x15 from address 0x7fb00000 is maintained. Booting from NAND in u-boot-7-2017-LSDK-17.12, the CPLD access is correct.

Thank you

[ufedor]

Please provide:

1) the processor to CPLD connection schematics as PDF

2) U-Boot log with the latest RCW

[carlos-m-ribeiro]

Hello,

If we reading all CPLD data in our custom board, using this board file:

=> md 7fb00000 20
7fb00000: 15151515 15151515 15151515 15151515 ................
7fb00010: 15151515 15151515 15151515 15151515 ................
7fb00020: 15151515 15151515 15151515 15151515 ................
7fb00030: 15151515 15151515 15151515 15151515 ................
7fb00040: 15151515 15151515 15151515 15151515 ................
7fb00050: 15151515 15151515 15151515 15151515 ................
7fb00060: 15151515 15151515 15151515 15151515 ................
7fb00070: 15151515 15151515 15151515 15151515 ................
=> md.b 7fb00000 80
7fb00000: 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 ................
7fb00010: 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 ................
7fb00020: 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 ................
7fb00030: 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 ................
7fb00040: 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 ................
7fb00050: 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 ................
7fb00060: 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 ................
7fb00070: 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 ................
=>

The u-boot log:

SoC: LS1023A Rev1.1 (0x87920911)
Clock Configuration:
CPU0(A53):1000 MHz CPU1(A53):1000 MHz
Bus: 300 MHz DDR: 1600 MT/s FMAN: 600 MHz
Reset Configuration Word (RCW):
00000000: 0610000a 0c000000 00000000 00000000
00000010: 34550002 00004012 40025000 c1002000
00000020: 00000000 00000000 00000000 0003cffc
00000030: 20004104 04102501 00000096 00000001
Model: LS1043A QDS Board
***********************************************
*** BOARD: AT16sxg, ALTICE LABS 2021 ***
***********************************************
BOOTING FROM...QSPI
I2C: ready
DRAM: Initializing DDR....
Detected UDIMM Fixed DDR on board
3.9 GiB (DDR4, 32-bit, CL=11, ECC off)
Using SERDES1 Protocol: 13397 (0x3455)
Waking secondary cores to start from fbd24000
All (2) cores are up.
Flash: 0 Bytes
NAND: fsl_ifc_chip_init: address did not match any chip selects
0 MiB
MMC: FSL_SDHC: 0
Loading Environment from SPI Flash... SF: Detected w25q256fw with page size 256 Bytes, erase size 4 KiB, total 32 MiB
OK
In: serial
Out: serial
Err: serial
Net: Using SerDes protocol 0x3455 for AT16sxg
SF: Detected w25q256fw with page size 256 Bytes, erase size 4 KiB, total 32 MiB
Fman1: Uploading microcode version 108.4.9
Could not get PHY for FSL_MDIO0: addr 4
Failed to connect
Could not get PHY for FSL_MDIO0: addr 5
Failed to connect
Could not get PHY for FSL_MDIO0: addr 1
Failed to connect
Could not get PHY for FSL_MDIO0: addr 6
Failed to connect
Could not get PHY for FSL_MDIO0: addr 7
Failed to connect
Could not get PHY for FSL_MDIO0: addr 0
Failed to connect
PCIe1: pcie@3400000 disabled
PCIe2: pcie@3500000 Root Complex: no link
PCIe3: pcie@3600000 Root Complex: no link
FM1@DTSEC1
Error: FM1@DTSEC1 address not set.
, FM1@DTSEC2
Error: FM1@DTSEC2 address not set.
, FM1@DTSEC3 [PRIME], FM1@DTSEC5
Error: FM1@DTSEC5 address not set.
, FM1@DTSEC6
Error: FM1@DTSEC6 address not set.
, FM1@DTSEC9
Error: FM1@DTSEC9 address not set.

Autoboot in 3 seconds

The RCW used:

Reset Configuration Word (RCW):
00000000: 0610000a 0c000000 00000000 00000000
00000010: 34550002 00004012 40025000 c1002000
00000020: 00000000 00000000 00000000 0003cffc
00000030: 20004104 04102501 00000096 00000001

Best regards

[ufedor]

Please use a digital scope and check activity of the address lines connected to the CPLD when read is attempted.

[carlos-m-ribeiro]

Hello,

But the address lines connected to the CPLD are the same using U-BOOT for NAND (generated from u-boot-7-2017-LSDK-17.12) where the CPLD read is correct.

Thank you

[ufedor]

What cfg_rcw_src is used for booting from NAND?

In the provided U-Boot log the IFC_MODE value is 0b000100101 - i.e. 16-bit NOR Flash, address shift left by 4, AVD before CS.

[carlos-m-ribeiro]

Hello,

The U-Boot log provided was obtained booting from QSPI. For the U-Boot from NAND, the RCW word used was:

#PBL preamble and RCW header
aa55aa55 01ee0100
# serdes protocol
0610000a 0c000000 00000000 00000000
34550002 00004012 e0106000 c1002000
00000000 00000000 00000000 0003cffc
20004101 04102501 00000096 00000001

Which the IFC_MODE value we should use to 32-bit NOR Flash?

Thank you

[carlos-m-ribeiro]

And for booting from NAND, the IFC_MODE is

0b100000110.

[ufedor]

It was previously suggested:

> Set this mode (NAND) in the RCW[IFC_MODE] when booting from QSPI.

but still some misunderstanding exists.

Please use 0b100000110 as IFC_MODE in the RCW located in the SPI Flash.

[carlos-m-ribeiro]

But when using 0b100000110 as IFC_MODE in the RCW located in the QSPI Flash, we cannot boot and we cannot see any log.

Thank you