LS102xA: PCIe ATU inbound configuration

[Tarek]

In our application, the FPGA is the only endpoint connected to the LS1021A SoC over PCIe bus.

From the FPGA we need to access CCSR and OCRAM areas as inbound memory read. The CCSR is at physical address 0x100 0000 and OCRAM at physical address 0x1000 0000.

We are going to use Flat PCI bus address mapping. So FPGA will use address 0x100 0000 for accessing CCSR and address 0x1000 0000 for OCRAM.

My question is do we have to program the ATU inbound to map PCI address 0x100 0000 to Physical address 0x100 0000 for CCSR and PCI address 0x1000 0000 to Physical address 0x1000 0000?

In other words, the Inbound Base and Target are exactly the same!

If we did not configure the ATU inbound are we still going to achieve the same effect?

Your help is highly appreciated.

Thanks,

Tarek

[ufedor]

The default behavior of the ATU when there is no TLP attribute match in the inbound direction, is to pass the transaction through.

[Tarek]

Thanks for the clarification. This answers my main question.

But this means the default behaviour does not protect the SoC internal registers? If I didn't configure the inbound ATU any PCI endpoint device can write any value to any chip register and corrupt the system! Right?

Is this not a security concern inherited by the default behaviour of the LS1021A Chip?

Thanks for your help.

[ufedor]

Sorry, my response was too short.

An iATU region has to be configured and enabled to make handling of inbound TLPs possible.

Please refer to the attached presentation.

[Tarek]

I've seen this presentation and it's very useful. It is very good at explaining how to configure the ATU. What id doesn't say if I have to configure it or not!

I think what you are saying is for any inbound TLP to work, the ATU inbound must be configured. Even if the mapping is one to one.

ATU inbound:

==========

For OCRAM ::: Base address = 0x1000 0000  - Target address = 0x1000 0000.

For DRAM    ::: Base address = 0x8000 0000  - Target address = 0x8000 0000.

Is that correct?

[ufedor]

> for any inbound TLP to work, the ATU inbound must be configured.

> Even if the mapping is one to one.

Your understanding is correct.

I agree that in your case it is convenient to configure two inbound regions.

[Tarek]

Thanks for your input.

The BSP you deliver only configures the ATU outbound as seen in the devicetree and there is no inbound configuration as far as I can tell.

This is the device tree configuration:

ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */

          0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /*non-prefetchable memory */

Outbound Region    BASE                  Target         Type

Region 1	0x40 0001 0000	0x0000 0000	Downstream I/O
Region 2	0x40 4000 0000	0x4000 0000	Non-prefetchable memory

We tried a memory read command from the FPGA to SoC DRAM by using the physical address of the DRAM in the 0x80000000 to 0xC0000000 range and that works fine.

I have dumped the ATU inbound registers and all values are 0x0.

So looks like your first answer "Transaction is pass through" is applicable: 

"The default behaviour of the ATU when there is no TLP attribute match in the inbound direction, is to pass the transaction through."

However, this is only for DRAM access. I am not sure about accessing areas outside the DRAM like OCRAM and CCSR.

Do you think the ATU inbound is configured in your BSP to access DRAM?

Can you please give me a pointer to the code that does this configuration so I can add the OCRAM and CCSR to it?

Thanks

[ufedor]

You are absolutely correct: if the inbound iATUs are not configured, the default setting will allow all the inbound transactions to be passed through. All the NXP SDKs for Layerscape processors are developed this way, no inbound iATUs configured.