LS1028A Serdes Lane A Phy change

[mkraj]

Dear NXP expert

1. Due to more ethernet port requirement, Planning to change SerDes lane A SGMII PHY with Microchip SGMII 5 port switch KSZ9477S.  Is it require any major. Is it require any major software change?

2. We are not using IEEE1588 or RGMII interfaces , Still is it required to give EC1_GTX_CLK125 input reference clock?

With Regards

Krishnam Raju M

[mkraj]

Dear  yipingwang

Thank you.

With Regards

Krishnam Raju m

[yipingwang · Accepted solution]

[1] Treat it as a PHY operating over the SGMII Interface. The Switch will direct any MDIO mgmt. to the appropriate port based on the PHY ADDR used.

[2] See AN12028 for the recommended termination of unused signals.