We did some more digging with the scope.
On the LS1028ARDB, the RESET_nREQ pin goes to an FPGA. On our board it only has a o pull-up as the datasheet suggested.
When I attempt to reboot, the RESET_nREQ asserts low and nothing else happens.
On the LS1028ARDB, the RESET_nREQ asserts low and then the FPGA pulls the nPORESET low, which causes the reboot.
So we attempted the obvious and tied these two pins together. This caused the board to no longer boot at all.
Next thing we tried was route the RESET_nREQ to an input of the power-supply monitor chip that controls the nPORESET signal, so that when RESET_nREQ asserts, the monitor chip will assert the nPORESET signal for several milliseconds.
This appears to work in our testing.
Question to NXP engineers is now, is this how it's supposed to work?
Is the maybe some application note on this reset signal that explains how these signals are supposed to work? The datasheet is rather vague about it.