- NXP designs to an attachment unit interface (AUI) specification (MII, GMII, RGMII, SGMII, etc.), so in most cases proper operation is achieved if the interface signal requirements (timings, IO levels, etc.) are met. This includes PHYless designs as well.
- Input Output Buffer Information Specification (IBIS) modeling can help determine signal degradation to/from our device across the interconnect.
- Actual medium support (copper, fiber, coax, etc) is dependent on the Medium Attachment Unit (MAU) connected to our device (PHY, Switch, FPGA, etc).
So, 100BASE-FX is not an interface supported by our SoCs.
SGMII with 8b/10b encoding is the best we have to offer to get 100Mbps with an optical connection.
Can the FPGA connect to the LS device via SGMII?
As a side note, naming conventions can get confusing. We do list a 1000BASE-X mode but this is really just SGMII with the rate-adaptation logic disabled.
