LS1021A board without the CPLD?

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LS1021A board without the CPLD?

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fzhang
Contributor II

What I am looking into is to use LS1021A with Altera Arria V on a main board. The tasks for LS1021A is to communicate with FPGA through PCIe x4, even configure FPGA through JTAG connections on PCIe. Also use the GigE to connect to a PC. USB, HDMI and SD card ports to LS1021A.

I looked at the Tower and IOT boards of this device. It seems more complicated than what I thought. First of all the CPLD controls some the power up and reset sequences, LCD display through HDMI and more. I don't know if it's possible to use the micro without the CPLD and not making things more complicated.

Any inputs are greatly appreciated!

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r8070z
NXP TechSupport
NXP TechSupport

Have a great day,

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Yes a LS1021A system without the CPLD is possible. The TWR CPLD is used to implement

1 System power and reset sequencing management

2 LCD 2-bit FDI to 1-bit conversion

3 IFC address/data multiplexed signals latch

4 Mux/demux function signal (for example, CAN3/4_TX/RX, LCD, and UCC)

5 Level shifter (for example, USB2 signals)

6 NOR bank selection logic

However, you will need for additional system logic. Most likely in your system (3, 4, 5, 6) will not needed. For example you can use NAND flash for the configuration and boot software (firmware). IFC NAND controller can be connected directly to NAND flash device.

In any case you will need to implement (1) i.e. add reset logic for the LS1021 reset signals, pull-ups/pull-downs on the POR configurations pins, the MC34VR500 helps with system power. The LS1021A does not provide HDMI port, so some glue logic and HDMI transmitter will be required (2).

It is not clear what do you mean as “even configure FPGA through JTAG connections on PCIe”. The PCIe slot has pins for JTAG, but the PCIe controller does not.

Please see also the application note AN4878 “QorIQ LS1021A Design Checklist” available on the NXP site.

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fzhang
Contributor II

Serguei, Thank you for the detail explanation.

I probably will keep the CPLD to do the same thing (~50% of the demo board) so that makes my life easier.

For the PCIe x4 connections, is there a reference design that I can use from NXP? I am looking at the reference manual now. Thanks,

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