LS1012A boot rom hangs

[User1046]

I am looking for some help trying to figure out a start up issue with a new LS1012A design.

On this new design, the boot rom loops forever while reading an 0x000000F0 at address 0x1ee_0118. The cfg_rcw_src is pulled high. I can program the RCW and single step through the boot rom code.

The 25MHz oscillator connected to EXTAL. Oscillator is running for 200ms before deasserting PORESET.

One other thing that I notice is that 0x1ee_0000 is FFBFFF4E on the design

For the FRWY dev board 0x1ee_0000 is FFBF7F22

[yipingwang]

By inspecting the reg dump, your system might boot up in hard-coded mode. Although the cfg_rcw_src is pulled up in the schematics, users still need to measure this pin's power level at deasserting PORESET to confirm the correct rcw src setting.

The hard-coded RCW contents
1. Register 0x01ee-0100 = 0x06000008 which matches with hard-coded SYS_PLL_RAT(4:1) and CGA_PLL1_RAT(6:1).
2. Register 0x01ee-0114 = 0x0c0000c0 which matches with hard-coded SRDS_PLL_REF_CLK_SEL_S1(2b11) and SerDes_INT_REFCLK(1b1)
3. Register 0x01ee-0000 = 0xffbfff4e, PORSR1[bit 2]=0b - hard-coded RCW source.

[User1046]

What would cause the internal boot loader to read in a 0xF0000000 (undefined boot device) instead of an 0x40000000 (qspi boot device) at 0x1ee_0000?

There is another clue, the value at register address 0x1ee_0000 (PORSR1; POR status register 1) is 0xFFBFFF4D instead of a 0xFFBF7F22. All but one bit is reserved in POR status register 1. That one bit is used to indicate what the RCW source is. A 0x0 means the RCW is hardcoded and a 0x1 means the RCW is in the QSPI. On reset deassert, our new design is sampling a 0. I have the cfg_rcw_src pulled up to 1.8V. The pin is single use; just pulled high.