In my PCB,LS1012A Serdes lane A:SGMII1,lane B:SGMII2,lane D:PCIE(Endpoint).
SD1_REF_CLK1_P/N PIN is provided 100Mhz from X86 DEMO.
The PCIE of X86 DEMO is configured to operate as a PCI Express Root Complex.
LS1012A is configured to operate as a Endpoint device.
But <QorIQ LS1012A Reference Manual >Page 234
Setting this bit to 0 is only supported with
SerDes protocol option (SRDS_PRTCL_S1) =
SGMII1 and SGMII2 can not work?
Solved! Go to Solution.
Proper operation of SGMII1 and SGMII2 cannot be guaranteed when LS1012A SerDes reference clock is provided by a PCIe RC because spread-spectrum can be used.